ATS'13

General Information
Symposium Overview News Program Highlight Committee Contact Us
The Symposium
Location Venue & Transportation Accommodation VISA Registration
Technical Program
Keynote & Invited Talks Tutorial Program JETTA Special Issue
Submissions
Call for Papers Electronic Paper Submission Author Kit
Sponsors
Sponsor List
Related Links
WRTLT'13

Tutorial

Tutorial 1
Title	Statistical Adaptive Test Methods Targeting "Zero Defect" IC Quality and Reliability
Presenter	Prof. Adit D. Singh Dept. of Electrical and Computer Engineering, Auburn University
Biography Adit D. Singh is James B. Davis Professor of Electrical and Computer Engineering at Auburn University, where he directs the VLSI Design and Test Laboratory. His technical interests span all aspects of VLSI test and reliability. He has published nearly two hundred research papers, served as a consultant for several major semiconductor companies, and holds international patents that have been licensed to industry. He has held leadership roles at international test conferences, including serving as General Chair of the 2000 IEEE VLSI Test Symposium, the 2003 IEEE Defect Based Test Workshop, and the 2004 IEEE Memory Test Workshop. He also serves on the editorial boards of IEEE Design and Test Magazine, and JETTA. Dr. Singh is a Fellow of IEEE, a Golden Core member of the IEEE Computer Society and is past chair of the IEEE Test Technology Technical Council. He can be reached at email: adsingh@auburn.edu Abstract Integrated circuits have traditionally all been tested identically in the manufacturing flow with little sharing of test results between the different test insertions. However, as the detection of subtle manufacturing flaws becomes ever more challenging and expensive in aggressively scaled nanometer technologies, innovative new statistical screening methods are being developed that attempt to improve test effectiveness and optimize test costs by subjecting “suspect” parts to more extensive testing, and also adaptively bring in additional tests that target the suspected failure mode. The idea is analogous to selective security screening approaches applied at airports. Such statistical methods fall into two broad categories: those that exploit the statistics of defect distribution on wafers, and those that exploit the correlation in the variation of process and performance parameters on wafers. This tutorial presents test methodologies that span both these categories, and illustrates their effectiveness with results from a number of recently published experimental studies on production digital and analog circuits from IBM, Intel and LSI Logic, Analog Devices and NXP Semiconductor. Commercial tools offered by a number of new companies that have emerged in the "Adaptive Test" space will also be discussed. Broadly, these aim provide to support for the sharing and leveraging of results from the different tests in the test flow for effective test adaptation and optimization.

Tutorial 2
Title	Testing TSV-Based 3D Stacked ICs
Presenter	Prof. Krishnendu Chakrabarty Dept. of Electrical and Computer Engineering, Duke University
Biography Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now Professor of Electrical and Computer Engineering at Duke University. He is also a Chair Professor at Tsinghua University, Beijing, China, a Visiting Chair Professor at National Cheng Kung University in Taiwan, and a Guest Professor at University of Bremen in Germany. Prof. Chakrabarty is a recipient of the National Science Foundation CAREER award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship from the Alexander von Humboldt Foundation, Germany, and several best paper awards at IEEE conferences. Prof. Chakrabarty’s current research projects include: testing and DFT; digital microfluidic biochips and cyberphysical systems; optimization of digital print and production system infrastructure. He has authored 12 books on these topics (with two more books in press), published over 430 papers in journals and refereed conference proceedings, and given over 190 invited, keynote, and plenary talks. He has also presented over 30 tutorials at major conferences such as ITC, DAC, ICCAD, DATE, ESWeek, SOCC, and ISCAS. Prof. Chakrabarty is a Fellow of IEEE, a Golden Core Member of the IEEE Computer Society, and a Distinguished Engineer of ACM. He served as a Distinguished Visitor of the IEEE Computer Society during 2005- 2007 and during 2010-2012, and as a Distinguished Lecturer of the IEEE Circuits and Systems Society during 2006-2007. Currently he serves as an ACM Distinguished Speaker, as well as a Distinguished Lecturer of the IEEE Circuits and Systems Society for 2012-2014. He served as the Editor-in-Chief of IEEE Design & Test of Computers during 2010-2012. Currently he serves as the Editor-in-Chief of ACM Journal on Emerging Technologies in Computing Systems. Prof. Chakrabarty is also an Associate Editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Computers, IEEE Transactions on Circuits and Systems II, and IEEE Transactions on Biomedical Circuits and Systems. He serves as an Editor of the Journal of Electronic Testing: Theory and Applications (JETTA). Abstract Three-dimensional stacked ICs offer dense integration of heterogeneous technologies with a small footprint. Interconnection of the various tiers by means of through-silicon vias (TSVs) promises to increase interconnect bandwidth and performance while lowering power and manufacturing cost. However, testing for manufacturing defects remains an obstacle and a potential showstopper before 3D ICs can become a reality. There are concerns about the cost, or even worse, feasibility of testing such TSV-based 3D chips. This tutorial will discuss challenges and solutions for 3D IC test. The tutorial will include test flows based on known-good Die (KGD) and known-good stack (KGS) testing, and the role of modular testing. It will cover new defects and tests for TSV-based interconnects, and testaccess challenges related to KGD and KGS testing. The speaker will also pre-bond test solutions that targets dies and TSVs. Finally, the speaker will cover a DfT architecture that supports modular post-bond testing.