Keynote & Invited Talks
- Keynote: Prof. Kwang-Ting (Tim) Cheng, UCSB
- Invited Talk I: Dr. Wu-Tung Cheng, Mentor Graphics
- Invited Talk II: Dr. William Wu Shen, TSMC
Keynote Speaker
Prof. Kwang-Ting Cheng |
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Title: Test Data Analytics - from Mathematical Tools to Applications |
Abstract:
There exist meaningful patterns in test data. Test data analytics,
which explores the hidden patterns and correlations in the test data,
has a wide range of applications such as reducing test time, improving
test quality, identifying outliers for diagnosis, discovering weak
links in the manufacturing process, and improving the robustness of
the design. There are clear benefits to formulate test problems as
data analysis problems and employ existing mathematical tools, as well
as develop additional supporting tools, in predictive analytics, data
mining, and statistical modeling for uncovering hidden patterns,
unknown correlations and other useful information in the production
test data. In the talk, we will describe some promising directions in
test data analytics and discuss some of their applications.
Biography:
Cheng received his Ph.D. in EECS from the University of California,
Berkeley in 1988. He worked at Bell Laboratories from 1988 to 1993 and
joined the faculty at the University of California, Santa Barbara in
1993 where he is currently Associate Vice Chancellor for Research and
Professor in ECE. He was the founding director of UCSB’s Computer
Engineering Program (1999-2002) and Chair of the ECE Department
(2005-2008). He held a Visiting Professor position at National
TsingHua Univ., Taiwan (1999), Univ. of Tokyo, Japan (2008), and Hong
Kong Univ. of Science and Technology (2012), an Adjunct Professor at
Peking University, China
(2003-2005) and
Adjunct Chair Professor at Zhejiang University, China (2012-present).
His current research interests include SoC design validation and test,
mobile embedded systems, and multimedia computing. Cheng currently
serves as Director for DoD/MURI Center for 3D hybrid circuits which
aims at monolithically integrating CMOS with high-density memristors.
He has published more than 350 technical papers, co-authored five
books, supervised 29 PhD dissertations, and holds 12 U.S.
patents in these areas.
Cheng, an IEEE fellow, received ten Best Paper Awards from various
IEEE conferences and journals. He has also received the 2004-2005 UCSB
College of Engineering Outstanding Teaching Faculty Award. He served
as Editor-in-Chief of IEEE Design and Test of Computers (2006-2009)
and was a board member of IEEE Council of Electronic Design
Automation’s Board of Governors, IEEE Computer Society’s Publication
Board, and working groups of International Technology Roadmap for
Semiconductors (ITRS). He has also served as General and Program Chair
for several international conferences including 2012 IEEE
International Test Conference.
Invited Talk Speakers
| Dr. Wu-Tung Cheng |
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Title: New Approaches to Improving Quality and Accelerating Yield Ramp to Meet Process Technology Disruptions |
Abstract:
Recent technology nodes have each brought about new process challenges that introduced manufacturing defects which required new manufacturing test, yield learning and physical failure analysis methods. This presentation takes a look back at a couple major recent process technology changes to understand how manufacturing test, diagnosis and yield analysis have evolved to address the challenges. The presentation will then take a look to the upcoming FinFET process technology and explore how test, diagnosis, and yield analysis will need to continue to evolve to address the expected quality and yield challenges of this significant change in process technology.
Biography:
Wu-Tung Cheng received the B.S. and M.S. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, R.O.C., in 1978 and 1982, respectively, and the Ph.D. degree in computer science from the University of Illinois at Urbana–Champaign, Urbana, IL, in 1985. From 1985 to 1990, he was with AT&T Bell Laboratories, Princeton, NJ, developing a test pattern generation system for digital circuits. From 1990 to 1993, he was a cofounder of CheckLogic System, Inc., leading a team to develop commercial test automation products. In 1993, CheckLogic was merged with Mentor Graphics Corporation, Wilsonville, OR. Since then, he has had various technical and management positions in areas of design for test, scan diagnosis and yield. He is currently a Chief Scientist and the director of Advanced Test Research. He has published over 125 research papers and co-invented 34 patents. He was an IEEE fellow since 2000.
| Dr. William Wu Shen |
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Title: 3DIC’s System Design Impact and Testing Needs |
Abstract:
The 3DIC vast interconnecting capabilities and ultra-short die to die distance can be fully explored for high bandwidth, low power applications. With the 3DIC memory family become standard last year, this also made a full computer system within 3DIC
During IC manufacture process, a logic die through test become KGD (Known Good Die) and ready to be assembled by next level process. Few KGDs through assemble process become KGS (Known Good System). For 3DIC KGD and KGS test, the 3D interconnection verifications are important topic and many challenges have been found and overcome. For example, uBump are small and fragile, they cannot be touched or probed. So interconnect joints have to be tested with on-die logic support before KGS steps. For this, a set of design guideline will be provided to designer aiming for better DfT (Design for Test) and Boundary Scan test results.
To manufacture 3DIC system with multiple dice, especially for a foreign die from third manufacture party, the challenges are grown. Even it is standard interface, it still may leave a lot uncertainties and need to be improved.
Here we shall introduce one of test vehicles using TSMC CoWoStm platform and using one of the JEDEC standard WideIO DRAM. We shall use it as example to explore 3DIC system advantages, design for test challenges and proposed solutions. Also we shall share a brief lesson learned from this Test Vehicle as well as some suggestions for future considerations.
Biography:
William (Bill) has worked in memory controller/system design area for more than 20 years. Experience background includes logic design, team leader for memory controller, memory-subsystem architect, lead system design engineer in multi-national companies, such as International Business Machine and LSI Corp.
Currently he is Senior Manager, Test Chip Design Verification Division, TSMC Corp. at Hsinchu, Taiwan. He also serves as Vice Chairman of JEDEC JC42.3B DRAM Features and Functions Letter Committee.
Bill has held both PHD and Master degree from Clarkson University, NY, U.S.A and BSEE degree from Taipei Institute of Technology, Taipei, Taiwan. Personal hobbies include reading, photography, fishing and audio amplify equipment.