| IEEE Asian Test Symposium > |
20th Asian Test Symposium, ATS'11
November 20-23, 2011
Hotel Crowne Plaza, Okhla, New Delhi, India
About this conference
20th ATS 2011 is the twentieth in this series of symposia started in 1992 devoted to testing, fault tolerant computing and the design of reliable circuits and systems. ATS is recognized as the main event in Asia that covers the many dimensions of testing and fault-tolerance. In 2011, the 20th Anniversary of the Asian Test Symposium will be celebrated in New Delhi, India and is of particular sinificance due to the rise of Asia, over the last several decades, in the areas of integrated circuit design and manufacturing, and electronic systems and software engineering, both of which embrace testing as a core technology. New Delhi, in particular, is a major player in India's computing industry with emerging "technology satellites" in nearby Noida and Gurgaon and the face of her new "modernity". At the same time, New Delhi, is the centerpiece of Indian culture, tradition and cuisine, having been at the helm of Indian history for centuries, dating back to the Mughal period and the British Raj.
Symposium Theme
The theme for ATS 2011 will be "Test Odyssey 2020: Testing Systems and Devices at the Peta and Nano Scales". This theme is inspired by the fact that technology is trending towards extremely high levels of integration at the package and chip levels, very high speeds of operation (> 100 GHz) and use of deeply scaled technology (approaching 10nm CMOS). In addition, a key test challenge will arise due to the ability to design complex systems such as robots that encompass sensors, communications systems, processors, transducers and enabling software. In addition to passing post-manufacture test procedures, such systems and relevant devices must exhibit fault-tolerance and survivability characteristics.
Topics of Interest (but are not limited to)
Original contributions in testing, fault tolerant and reliable computing are solicited. Topics of interest include, but are not limited to, the following categories:
Automatic Test Pattern Generation (ATPG)
Boundary Scan
Test Compression
Online Test
Temperature/Power-aware Test
Design-for-testability (DFT)
Microprocessor Test
Mixed signal and Analog Test
Memory Test
System-in-package (SiP)/ 3D Test
Test Quality and Reliability
Design Validation/Silicon Debug
Fault Modeling/Defect Based Test
Fault Simulation/Diagnosis
Software Testing
Board and System Test
Other
Important Dates/Deadlines
Papers
Special Session proposals
Tutorial proposals
Exhibition/Booth proposals
Notification of acceptance
Camera-ready paper due date
Organizing Committe
• General Chairs
◦ Abhijit Chatterjee, Georgia Tech {chat@ece.gatech.edu}
◦ Amit Patra, IIT Kharagpur {amit@ee.iitkgp.ernet.in}
• Program Chairs
◦ Sandip Kundu, UMass Amherst {kundu@ecs.umass.edu}
◦ Srivaths Ravi, Texas Instruments, India {srivaths.ravi@ti.com}
• Finance Chair
◦ Virendra Singh {virendra@computer.org}
◦ Gulshan Dua, Freescale Semiconductor, Finance Co-Chair
• Local Organization Chair
◦ Jaswinder Ahuja, Cadence India {jassi@cadence.com}
◦ Pankaj Jalote, IIIT Delhi {jalote@cse.iitd.ernet.in}, Organizing Co-chair
• Publications Chair
◦ S. Sur-Kolay, ISI, Kolkata {ssk@isical.ac.in}
• AV Chair
◦ Ashok Kumar Sihag, Gautam Buddha University, {ashoksihag@gmail.com}
• European Liaison
◦ M. Renovell {renovell@lirmm.fr}
• US Liaison
◦ V. Agrawal, Auburn University {vagrawal@eng.auburn.edu}
• Publicity Chair & Web Manager
◦ Aswin Sreedhar, Intel, US {aswin.sreedhar@intel.com}
---------------------------------------
Program Committe
• Jacob Abraham, University of Texas, Austin USA
• Vishwani Agarwal, Auburn University USA
• Karim Arabi, Qualcomm USA
• Kedarnath Balakrishnan, AMD
• Bhargab B. Bhattacharya, Indian Statistical Institute India
• Swarup Bhunia, Case Western Reserve University USA
• Kirshnendu Chakrabarty, Duke University USA
• Krishna Chakravadhanula, Cadence Design Systems
• Sreejit Chakravarty, LSI Logic USA
• Chia-Tso Chao, National Chiao Tung University Taiwan
• Santanu Chattopadhyay, Indian Institute of Technology, Kharagpur India
• Dipanwita Roy Chowdhury, Indian Institute of Technology, Kharagpur India
• Vivek Chickermane, Cadence Design Systems USA
• CP Ravikumar, Texas Instruments India
• Varadarajan Devanathan, Texas Instruments India
• Hideo Fujiwara, Nara Institute of Science and Technology (NAIST) Japan
• Rajesh Galivanche, Intel USA
• Patrick Girard, LIRMM/CNRS France
• Elena Gramatova, Slovak Academy of Sciences Slovakia
• Sandeep Gupta, University of Southern California USA
• Kazumi Hatayama, Nara Institute of Science and Technology, Japan
• Shi-Yu Hang, National Tsing Hua University
• Masaki Hashizume, University of Tokushima Japan
• Michiko Inoue, Nara Institute of Science and Technology (NAIST) Japan
• Tomoo Inoue, Hiroshima City University, Japan
• Seiji Kajihara, Kyushu Institute of Technology, Japan
• Rohit Kapur, Synopsys USA
• Erik Larsson, Linkoping University Sweden
• Kuen-Jong Lee, National Cheng Kung University, Taiwan
• Huawei Li, Institute of Computing Technology, CAS China
• Xiaowei Li, Institute of Computing Technology, CAS China
• Erik Jan Marinissen, IMEC Belgium
• Cecilia Metra, University of Bolgna, Italy
• Subashish Mitra, Stanford University, USA
• Nilanjan Mukerjee, Mentor Graphics USA
• Fidel Muradali, National Semiconductors, USA
• Sule Ozev, Arizona State University, USA
• Rubin Parekhji, Texas Instruments India
• Srinivas Patil, Intel USA
• Ilia Polian, University of Passau Germany
• Hafizur Rahaman, Bengal Engineering and Science University India
• Sudhakar M. Reddy, University of Iowa USA
• Kewal K. Saluja, University of Wisconsin-Madison USA
• Yasuo Sato, Kyushu Institute of Technology Japan
• Indranil Sengupta, Indian Institute of Technology, Kharagpur India
• Adit Singh, Auburn University USA
• Virendra Singh, India Institute of Science India
• Mani Soma, University of Washington, USA
• Chau-Chin Su, National Central University, Taiwan
• Nagesh Tamarapalli, AMD India
• Mohammad Tehranipoor, University of Connecticut USA
• Nur Touba, University of Texas, Austin USA
• Kamakoti V, Indian Institute of Technology, Chennai India
• Li-C. Wang, University of California, Santa Barbara USA
• Xiaoqing Wen, Kyushu Institute of Technology Japan
• Dong Xiang, Tsinghua University, China
• Shiyi Xu, Shanghai University, China
• Said Hamdioui, Delft University of Technology, Netherlands
|
||||||||