| IEEE Asian Test Symposium > |
13th Asian Test Symposium, ATS'04
2004 IEEEAsian Test Symposium
November 15-17, 2004
Caesar Park Hotel, Kenting, Taiwan
SCOPE
Original contributions on VLSI testing are solicited. Topics of interest include, but are not limited to, the following categories:
1. Test generation & fault simulation
2. Design for testability
3. Fault diagnosis
4. Analog & mixed-signal testing
5. Memory testing
6. Wafer-level testing
7. System-On-A-Chip testing
8. Integration of design and test
9. Software testing
10. CPU testing
11. Failure analysis & fault modeling
12. Built-in self-test
13. Fault tolerance & error correction
14. Functional testing
15. IDDQ testing
16. Test economics
17. P1500 & boundary scan
18. Test experience in industry
19. Automatic test equipment
20. Yield Enhancement
SUBMISSION
Submission should be made electronically via the PDF format at web site ATS'04. In case of hardship,
one may seek help by sending an email to ats04@larc.ee.nthu.edu.tw.
A submission should contain a complete manuscript of less than 5000 words, an abstract of 50-200 words, and a separate cover page,
clearly indicating (1) the title of the paper, (2) the affiliation of each author,
(3) the contact author (including the postal and e-mail addresses), and (4) the categories of the topic.
A submission will be considered as evidence that once accepted the author(s) will prepare the final manuscript
in time for being included in the proceedings and will present the paper at the symposium.
IMPORTANT DATES
Deadline for submission : April 25, 2004
Notification of acceptance : July 1, 2004
Deadline for final manuscript : Aug. 20, 2004
ORGANIZING COMMITTEE
GENERAL CO-CHAIRS
Kuen-Jong Lee,
National Cheng-Kung Univ., Taiwan
Email: kjlee@mail.ncku.edu.tw
Chau-Chin Su,
National Chiao-Tung Univ., Taiwan
Email: ccsu@cn.nctu.edu.tw
PROGRAM CO-CHAIRS
Shi-Yu Huang,
National Tsing-Hua Univ., Taiwan
E-mail: syhuang@ee.nthu.edu.tw
Ming-Der Shieh,
National Cheng-Kung Univ., Taiwan
E-mail: shiehm@mail.ncku.edu.tw
FINANCE CHAIR
Tsin-Yuan Chang,
National Tsing-Hua Univ., Taiwan
LOCAL ARRANGEMENTS CHAIR
Jin-Hua Hong,
National Univ. of Kaohsiung, Taiwan
SECRETARIAT
Chih-Tsun Huang,
National Tsing-Hua Univ., Taiwan
REGISTRATION CHAIR
Shyue-Kung Lu,
Fu-Len Catholic Univ., Taiwan
PUBLICATIONS CHAIR
Jing-Jia Liou,
National Tsing-Hua Univ., Taiwan
PUBLICITY CHAIR
Michel Renovell,
LIRMM, France
INDUSTRIAL ARRANGEMENTS CHAIR
Wen-Ching Wu,
Industrial Tech. Research Inst., Taiwan
TUTORIALS CHAIR
Jwu-E Chen,
National Central University, Taiwan
NORTH AMERICAN LIAISON
Xiaoqing Wen,
Kyushu Institute of Technology, Japan
EUROPEAN LIAISON
Zebo Peng,
Linkoping Univ., Sweden
PROGRAM COMMITTEE
Jacob A. Abraham, University of Texas at Austin, USA
Vishwani D. Agrawal, Auburn University, USA
Robert Aitken, Artisan Components, Inc., USA
Melvin A. Breuer, University of Southern California, USA
Krishnendu Chakrabarty, Duke University, USA
Parimal Pal Chaudhuri, Indian Institute of Technology, India
Kwang-Ting Cheng, University of California, Santa Barbara, USA
Wu-Tung Cheng, Mentor Graphics Corp., USA
Serge Demidenko, Massey University, New Zealand
Hideo Fujiwara, Nara Institute of Science and Technology, Japan
Kiyoshi Furuya, Chuo University, Japan
Kazumi Hatayama, Renesas Technology Corp., Japan
Michael Hsiao, Department of ECE, Virginia Tech, USA
Andre Ivanov, University of British Columbia, Canada
Kazuhiko Iwasaki, Tokyo Metropolitan University, Japan
Wen-Ben Jone, University of Cincinnati, USA
Jing-Yang Jou, National Chiao Tung University, Taiwan
Seiji Kajihara, Kyushu Institute of Technology, Japan
Bozena Kaminska, Fluence Technology, USA
Christian Landrault, LIRMM, France
Chung-Len Lee, National Chiao-Tung University, Taiwan
Xiaowei Li, Institute of Computing Technology, Chinese Academy of Sciences, China
Erik Jan Marinissen, Philips Research Laboratories, The Netherlands
Edward J. McCluskey, Stanford University, USA
Yinghua Min, Institute of Computing Technology, CAS, China
Yukiya Miura, Tokyo Metropolitan University, Japan
Alex Orailoglu, University of California at San Diego, USA
Paolo Prinetto, Politecnico di Torino, Italy
Janusz Rajski, Mentor Graphics Corp., USA
Sudhakar M. Reddy, University of Iowa, USA
Kewal K. Saluja, University of Wisconsin-Madison, USA
Jacob Savir, New Jersey Institute of Technology, USA
Sharad C. Seth, University of Nebraska-Lincoln, USA
Meng-Lieh Sheu, National Chi Nan University, Taiwan
Mani Soma, University of Washington, USA
Hiroshi Takahashi, Ehime University, Japan
Sying-Jyan Wang, National Chung Hsing University, Taiwan
Li-C Wang, University of California, Santa Barbara, USA
Ching-Long Wey, Michigan State University, USA
Tom W. Williams, Synopsys Inc., USA
Cheng-Wen Wu, National Tsing Hua University, Taiwan
Shiyi Xu, Shanghai University, China
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2004 TECHNICAL PROGRAM
Date
Time
Sessions
Nov. 15
(Mon.)
9:00-12:00
Tutorial A1
(Thomas Warwick ¢w Signal Integrity, Jitter, and Timing Accuracy: The Basics of High Performance Test Measurements)
Tutorial B1
(Dr. Saghir Shaikh & Salem Abdennadher ¢w Boundary Scan Testing of Advanced Digital Networks: IEEE Std. 1149.6 Demystified)
12:00-13:30
Lunch
13:30-16:30
Tutorial A2
(Thomas Warwick ¢w Signal Integrity, Jitter, and Timing Accuracy: The Basics of High Performance Test Measurements)
Tutorial B2
(Dr. Saghir Shaikh & Salem Abdennadher ¢w Boundary Scan Testing of Advanced Digital Networks: IEEE Std. 1149.6 Demystified)
Nov. 16
(Tues.)¡@
8:30-8:40
Opening Ceremony
8:40-9:30
Keynote Speech
(Dr. Bernd Koenemann ¢w Defects: Whose Fault Are They?)
9:30-10:20
Invited Talk
(Prof. Melvin Breuer ¢w Error-Tolerance and Related Test Issues)
10:20-10:40
Coffee Break
10:40-12:00
Session A1
SOC Testing
Session B1
Low-Power Testing
Session C1
Analog BIST
12:00-13:30
Lunch
13:30-14:50
Session A2
Advanced DFT
Session B2
Fault Analysis
Session C2
Cross-Talk Testing
15:20-21:00
Social Program
Nov. 17
(Wed.)¡@
9:00-10:20
Session A3
Functional Testing
Session B3
Logic BIST
Session C3
Fault Diagnosis
10:20-10:40
Coffee Break
10:40-12:20
Session A4
SOC Test Scheduling
Session B4
Memory Testing
Session C4
Analog Testing
12:20-13:30
Lunch
13:30-14:50
Session A5
Testable Design
Session B5
Testability Analysis
Session C5
Yield and Reliability
14:50-15:10
Coffee Break
15:10-16:30
Session A6
Fault Tolerance
Session B6
FPGA Testing & Test Reduction
Session C6
Delay Testing
¡@
--------------------------------------------------------------------------------------------------------------Session A1: SOC Testing
Chair: Erik Larsson, Linköping University, Sweden
A1-1 Multi-frequency Test Access Mechanism Design for Modular SOC Testing
Q. Xu, N. Nicolici, McMaster University, Canada
A1-2 Rapid and Energy-Efficient Testing for Embedded Cores
Y. Han, Y. Hu, H. Li, X. Lee, A. Chandra, Institute of Computing Technology, Chinese Academy of Sciences, China
A1-3 Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy
J. Xing, H. Wang, S. Yang, Department of Automation, Tsinghua University, Beijing, China
A1-4 Adding Testability to an Asynchronous Interconnect for Globally-Asynchronous, Locally-Synchronous Systems-on-Chip
A. Efthymiou, J. Bainbridge, D. A. Edwards, University of Manchester, Greece
Session B1: Low-Power Testing
Chair: Chien-Mo James Li, National Taiwan University, Taiwan
B1-1 Test Power Reduction with Multiple Capture Orders
K.-J. Lee, S.-J. Hsu, C.-M. Ho, Dept. of EE, National Cheng Kung University, Taiwan
B1-2 Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths
Z. You, K. Yamaguchi, M. Inoue, J. Savir, H. Fujiwara, Nara Institute of Science and Technology, Japan
B1-3 Low Power BIST with Smoother and Scan-Chain Reorder
N.-C. Lai, Y.-H. Fu, S.-J. Wang, Institute of Computer Science, National Chung-Hsing University, Taiwan
B1-4 Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction
Y. Higami, S. Kajihara, S. Y. Kobayashi, Ehime University, Japan
Session C1: Analog BIST
Chair: Michel Renovell, LIRMM, France
C1-1 A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-To-Digital Converters
H.-W. Ting, B.-D. Liu, S.-J. Chang, Department of Electrical Engineering, National Cheng Kung University, Taiwan
C1-2 A New BIST Scheme Based on a Summing-Into-Timing-Signal Principle with Self Calibration for the DAC
G.-X. Chen, C.-L. Lee, J.-E. Chen, Department of Electronics Engineering, National Chiao Tung University, Taiwan
C1-3 A Sigma-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor
H.-C. Hong, C.-W. Wu, K.-T. Cheng, Dept. of Electrical and Control Engineering, National Chiao Tung University, Taiwan
C1-4 A Built-In Loopback Test Methodology for RF Transceiver Circuits using Embedded Sensor Circuits
S. Bhattacharya, A. Chatterjee, Georgia Inst of Technology, Indian
Session A2: Advanced DFT
Chair: Der-Chen Huang, National Chung-Hsing University, Taiwan
A2-1 Multiple Scan Tree Design with Test Vector Modification
K. Miyase, S. Kajihara, S. M. Reddy, Department of Computer Sciences and Electronics, Kyushu Institute of Technology, Japan
A2-2 An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains
J.-C. Rau, C.-H. Lin, J.-Y. Chang, Dept. of EE, Tamkang University, Taiwan
A2-3 Scan-Based BIST Using an Improved Scan Forest Architecture
D. Xiang, M.-J.Chen, Y.-L. Wu, Tsinghua University, China
A2-4 The Efficient Multiple Scan Chain Architecture Reducing Test Time and Power Dissipation
I.-S. Lee, T. Ambler, Y. M. Hur, University of Texas at Austin, Korea
Session B2: Fault Analysis
Chair: Yoshinobu Higami, Ehime University, Japan
B2-1 Testing for Missing-Gate Faults in Reversible Circuits
J. P. Hayes, I. Polian, B. Becker, Albert-Ludwigs-University, Germany
B2-2 Properties of Maximally Dominating Faults
I. Pomeranz, S. M. Reddy, Purdue University, USA
B2-3 IDDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment
M. Hashizume, D. Yoneda, H. Yotsuyanagi, T. Tada, T. Koyama, I. Morita, T. Tamesada, Department of Electrical and Electronics Engineering,
Faculty of Engineering, The Univ. of Tokushima, Japan
B2-4 High Level Fault Injection for Attack Simulation in Smart Cards
K. Rothbart, U. Neffe, C. Steger, R. Weiss, E. Rieger, A. Mühlberger, Graz University of Technology, Austria
Session C2: Cross-Talk Testing
Chair: Hiroshi Takahashi, Ehime University, Japan
C2-1 Efficient Identification of Crosstalk Induced Slowdown Targets
S. Nazarian, S. K. Gupta, M. A. Breuer, USC, USA
C2-2 Modeling and Testing Crosstalk Faults in Inter-Core Interconnects Including Tri-State and Bi-Directional Nets
W. Sirisaengtaksin, S. K. Gupta, USC, USA
C2-3 A New Path Delay Test Scheme Based on Path Delay Inertia
C.-L. Chen, C.-L. Lee, Department of Electronics Engineering, National Chiao Tung University, Taiwan
C2-4 A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI
K. S.-M. Li, C.-L. Lee, C.-C. Su, J.-E. Chen, Department of Electronics Engineering, National Chiao Tung University, Taiwan
Session A3: Functional Testing
Chair: Debesh K. Das, Jadavpur University, India
A3-1 Efficient Template Generation for Instruction-Based Self-Test of Processor Cores
K. Kambe, M. Inoue, H. Fujiwara, Nara Institute of Science and Technology, Japan
A3-2 Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores
S. Shamshiri, H. Esmaeilzadeh, Z. Navabi, University of Tehran, Iran
A3-3 A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA
C.-L. Chuang, D.-J. Lu, C.-N. Liu, National Central University Department of Electrical Engineering, Taiwan
A3-4 A Systematic Way of Functional Testing for VLSI Chips
S. Xu, Shanghai University, China
Session B3: Logic BIST
Chair: Kiyoshi Furuya,Chuo University, Japan
B3-1 Weighted Pseudo-Random BIST for N-detection of Single Stuck-At Faults
C. Yu, S. M. Reddy, I. Pomeranz, ECE Dept., University of Iowa, USA
B3-2 A BIST Approach to On-Line Monitoring of Digital VLSI Circuits
S. Biswas, S. Mukhopadhyay, A. Patra, Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, Indian
B3-3 Seed Selection Procedure for LFSR-based BIST with Multiple Scan Chains and Phase Shifters
M. Arai, H. Kurokawa, K. Ichino, S. Fukumoto, K. Iwasaki, Graduate School of Engineering, Tokyo Metropolitan University, Japan
B3-4 Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults
S. Das, A. Kundu, B. K. Sikdar, CST, B. E. College, Indian
Session C3: Fault Diagnosis
Chair: Shyue-Kung Lu, Fu-Len Catholic University, Taiwan
C3-1 Compactor Independent Direct Diagnosis
W.-T. Cheng, K.-H. Tsai, Y. Huang, N. Tamarapalli, J. Rajski, Mentor Graphics Corporation, USA
C3-2 Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits
S. Ghosh, K.-W. Lai, W.-B. Jone, S.-C. Chang, University of Cincinnati, USA
C3-3 Enhancing BIST Based Single/Multiple Stuck-At Fault Diagnosis by Ambiguous Test Set
H. Takahashi, Y. Yamamoto, Y. Higami, Y. Takamatsu, Ehime University, Japan
C3-4 Failure Analysis of Open Faults by Using Detecting /Un-detecting Information on Tests
Y. Sato, H. Takahashi, Y. Higami, Y. Takamatsu, Ehime University, Japan
Session A4: SOC Test Scheduling
Chair: Chih-Tsun Huang, National Tsing-Hua University, Taiwan
A4-1 Hybrid BIST Test Scheduling Based on Defect Probabilities
Z. He, G. Jervan, Z. Peng, Linköping University, Sweden
A4-2 Pair Balance-Based Test Scheduling for SOCs
Y. Hu, Y.-H. Han, H.-W. Li, T. Lv, X.-W. Li, Information Network Laboratory,
Institute of Computing Technology, Chinese Academy of Sciences, China
A4-3 RAIN : RAndom INsertion Scheduling Algorithm for SoC Test
J. B. Im, S. Chun, G. Kim, J. H. An, S. Kang, Yonsei University, Korea
A4-4 March Based Memory Core Test Scheduling for SOC
W.-L. Wang, Department of Electronic Engineering, Cheng Shiu University, Taiwan
A4-5 An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
S. Edbom, E. Larsson, Linköping University, Sweden
Session B4: Memory Testing
Chair: Wu-Tung Cheng, Mentor Graphics Corporation, USA
B4-1 On Test and Diagnostics of Flash Memories
C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, C.-W. Wu, National Tsing Hua University, Taiwan
B4-2 Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution
L.Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, S. Borri, M. Hage-Hassan, LIRMM, Universite´ de Montpellier II, France
B4-3 A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier
Y.-M. Sheng, M.-J. Hsiao, T.-Y. Chang, Dept. of EE, National Tsing Hua Uinv., Taiwan
B4-4 An Efficient Diagnosis Scheme for Random Access Memories
J.-F. Li, C.-D. Huang, Department of EE, National Central University, Taiwan
B4-5 Evaluation of Intra-Word Faults in Word-Oriented RAMs
S. Hamdioui, J. D. Reyes, Z. Al-Ars, Philips Semiconductor Crolles R&D, France
Session C4: Analog Testing
Chair: Christian Landrault, LIRMM, France
C4-1 Low-Cost Analog Signal Generation Using A Pulse-Density Modulated Digital ATE Channel
J. Rivoir, Agilent Technologies, Germany
C4-2 A Low-Cost Diagnosis Methodology for Pipelined A/D Converters
C.-H. Huang, K.-J. Lee, S.-J. Chang, Dept. of EE, National Cheng Kung University, Taiwan
C4-3 Reconfiguration for Enhanced Alternate Test (REALTEST) of Analog Circuits
G. Srinivasan, S. Goyal, A. Chatterjee, Georgia Institute of technology, USA
C4-4 Dynamic Analog Testing via ATE Digital Test Channels
C.-C. Su, C.-S. Chang, H.-W. Huang, D.-S. Tu, C.-L. Lee, C.-H. Lin, Natsional Chiao Tung University, Taiwan
Session A5: Testable Design
Chair: Shiyu Xu, Shanghai University, China
A5-1 Design and Implementation of Self-Testable Full Range Window Comparator
M. Wong, Y. Zhang, The Hong Kong Polytechnic University, China
A5-2 Efficient Test Methodologies for Conditional Sum Adders
J.-F. Li, C.-C. Hsu, Department of EE, National Central University, Taiwan
A5-3 A Novel Approach for On-line Testable Reversible Logic Circuit Design
D.-P. Vasudevan, P. K. Lala, and P. Parkerson, University of Arkansas, USA
A5-4 Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores
S. Das, B. K. Sikdar, P. P. Chaudhuri, Bengal Engineering College (DU), India
Session B5: Testability Analysis
Chair: Ching-Hwa Cheng, Feng-Chia University, Taiwan
B5-1 Circuit Width Based Heuristic for Boolean Reasoning
G. Li, X. Li, Institute of Computing Technology, Chinese Academy of Sciences, China
B5-2 Max-Testable Class of Sequential Circuits Having Combinational Test Generation Complexity
D. K. Das, T. Inoue, S. Chakraborty, H. Fujiwara, Jadavpur University, India
B5-3 Classification of Sequential Circuits Based on tk Notation
C. Y. Ooi, H. Fujiwara, Nara Institute of Science and Technology, Japan
B5-4 Detection of Reconvergent Branch Pairs
E. Edirisuriya, S. Xu , Shanghai University, China
Session C5: Yield and Reliability
Chair: Jwu-E Chen, National Central University, Taiwan
C5-1 Burn-In Stress Test of Analog CMOS ICs
C.-L. Wey, M.-Y. Liu, National Central University, Taiwan
C5-2 Fail Pattern Identification for Memory Built-In Self-Repair
R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, Y.-J. Chang, Department of Electrical Engineering,
National Tsing Hua University, Taiwan
C5-3 Reduce Yield Loss in Delay Defect Detection in Slack Interval
H. Yan, A. D. Singh, Electrical & Computer Engineering Department, Auburn University, USA
C5-4 Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing
C.-Y. Huang, C.-T. Lin, Department of Computer Science, National Tsing Hua University, Taiwan
Session A6: Fault Tolerance
Chair: Xiaowei Li, Chinese Academy of Sciences, China
A6-1 Intelligible Test Techniques to Support Error-Tolerance
M. Breuer, University of Southern Calif., USA
A6-2 Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment
J.-M. Yang, D.-F. Zhang, X.-D. Yang, Hunan University, China
A6-3 Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion
C.-C. Sue, J.-Y. Yeh, Dep. of CSIE, National Cheng Kung University, Taiwan
A6-4 On Improvement in Fault Tolerance of Hopfield Neural Networks
N. Kamiura, T. Isokawa, N. Matsui, Department of Electrical Engineering and Computer Sciences,
Graduate School of Engineering, University of Hyogo, Japan
Session B6: FPGA Testing and Test Reduction
Chair: Terumine Hayashi, Mie University, Japan
B6-1 Multiple Fault Detection and Diagnosis Techniques for Lookup Table FPGA's
S.-K. Lu, H.-C. Wu, S.-J. Yan, Y.-C. Tsai, Department of Electronic Engineering, Fu Jen Catholic University, Taiwan
B6-2 Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study
D. Han, A. Chatterjee, Georgia Institute of Technology, USA
B6-3 A Test Decompression Scheme for Variable-Length Coding
H. Ichihara, M. Ochi, M. Shintani, T. Inoue, Hiroshima City University, Japan
B6-4 Alternative Run-Length Coding through Scan Chain Reconfiguration
for Joint Minimization of Test Data Volume and Power Consumption in Scan Test
Y. Shi, S. Kimura, N. Togawa, M. Yanagisawa, T. Ohtsuki, Waseda Univ., Japan
Session C6: Delay Testing
Chair: Kazumi Hatayama, Renesas Technology Corporation, Japan
C6-1 Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects
L. Wang, S. K. Gupta, M. A. Breuer, University of Southern California, USA
C6-2 A Post-Processing Procedure of Test Enrichment for Path Delay Faults
I. Pomeranz, S. M. Reddy, Purdue University, USA
C6-3 Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing
H.-F. Ko, N. Nicolici, McMaster University, Canada
C6-4 Analysis and Attenuation Proposal in Ground Bounce
A. Zenteno, M. Renovell, National Institute of Astrophysics, Optics and Electronics-INAOE, Europe
¡@
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