| IEEE Asian Test Symposium > |
8th Asian Test Symposium, ATS'99
------------------------------------------------------------------------
ATS'99
CALL FOR PAPERS
The Eighth Asian Test Symposium
November 16-18, 1999, Hotel Equatorial Shanghai, China
------------------------------------------------------------------------
Sponsored by
The IEEE Computer Society Test Technology Technical Council
In Co-Operation with
Shanghai University
Computer Federation of China
Fault-tolerant Computing Technical Committee
National Natural Science Foundation of China
SCOPE
The Asian Test symposium explores emerging trends and novel concepts in testing of Computer system, board and component,
it provides an annual international forum for specialists from all over the world.
Topics of interest include, but are not limited to:
New ATPG Techniques
Diagnosis and Validation
Built-in Self-Testing
Scan & Boundary Scan
Sequential Test
Delay Fault & Memory Test
Design verification
Iddq Test
Analog Circuit Test
Networking Test
Software Test
Design for Testability
Concurrent Checking & Fault Tolerance
On-line Testing
SYMPOSIUM SCHEDULE
Submission deadline: April 1, 1999
Notification of acceptance: June 15, 1999
Camera-ready copy: August 1, 1999
SUBMISSIONS
The Program Committee invites authors to submit original, unpublished papers (full papers or extended summaries) and panel proposals.
Clearly describe the nature of the work, explain its significance, highlight novel features, and describe its current status.
The submission should not exceed 20 double-space pages including figure.
On the title page, please include: name, affiliation, mailing address, phone/fax number, and E-mail address of all authors,
an abstract of 50 words, and suggested topics.
Identify a contact author.
Please submit by mail five copies of the complete manuscript no later than April 1, 1999 to:
Shiyi Xu, ATSÕ99 Program Chair
Department of Computer Science
Shanghai University
Shanghai, China, 201800
Tel: +86-21-63287359
Fax: +86-21-59529932
E-mail: syxu@fudan.ac.cn
The submissions will be considered evidence that upon acceptance the author(s)
will prepare the final manuscript in time for inclusion in the proceedings
and will present the paper at the Symposium.
-----------------------------------------------------------------------
Organizing Committee
General Co-Chair
Ben M.Y.Hsiao
IBM Corporation USA
mhsiao@cn.ibm.com
Y.K. Malaiya
Colorado State Univ. USA
malaiya@cs.colostate.edu
Program Chair
Shiyi Xu
Shanghai University, China
syxu@fudan.ac.cn
Financial Chair
Ying Zhou
Shanghai University, China
stanley@public.sta.net.cn
Publication Chair
Huaikou Miao
Shanghai University, China
hkmiao@ats99.org
Publicity Chair
WeiKang Huang
Fudan University, China
wkhuang@fudan.edu.cn
Local Arrangement Chair
Wei Qin
Shanghai University, China
weiqin@ats99.org
Registration Chair
Jianwen Chen
Shanghai University, China
stanley@public.sta.net.cn
Secretary
Liangjun Fei
Shanghai University, China
lifei@ats99.org
Ex Officio
Group Chair, Asian Activities
TTTC, IEEE Computer Society
Asian Test Subcommittee Chair
Kozo Kinoshita
Osaka University, Japan
kozo@apleng.osaka-u.ac.jp
Program Committee
J.A.Abraham
J.Gao
K.J.Lee
Ad.J.Van de Goor
Y.Wu
V.D. Agrawal
D.S.Ha
Z.Li
P.Varma
T.Yamada
A.Bondavalli
H.Hiraishi
Y.Min
D.Wang
S.Yang
S.Chakravarty
S.J.Hong
P.Praneetpolgrang
W.Wang
X.Yang
C.L.Chen
A.Ivanov
S.M.Reddy
X.Wen
M.Yoshida
X. Chen
T.KiKuno
J.Savir
W.Wong
D.Zhang
S.Demideno
Y.Koga
L.Shen
M.W.T.Wong
H.Fujiwara
C.L.Lee
D.Siewiorek
C.W.Wu
K.Furuya
I.Lee
Y.Takamatsu
R.Wu
------------------------------------------------------------------------
Technical Program
1st Day - Tuesday Nov.16, 1999
2nd Day; 3rd Day
8:30-9:30
Plenary Session
Welcome message: Ben M.Y. Hsiao / Y.K. Malaiya Co-General Chair.
Keynote address: Build-in Self-test Past, Present and Future, Jacob Savir, New Jersey Ins. of Technology
Program introduction: S. Xu, Program Chair
9:30-9:50
Coffee Break
9:50-12:00
1A
ATPG Related Approaches (I)
Chair: Christian Landrault, LIRMM, France
1A.1
A Method of Test Generation for Weakly Testable Data Paths Using
Test Knowledge Extracted from RTL Description
Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara - Nara Institute of
Science and Technology, Japan
1A.2
Automatic Test Pattern Generation for Improving the Fault Coverage
of Microprocessors
Junichi Hirase, Shinichi Yoshimura, Tomohisa Sezaki - Matsushita
Electric Industrial Co. Ltd., Japan
1A.3
On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits
Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko - Kyushu
Institute of Technology, Japan
1A.4
Identification of Feedback Bridging Faults with Oscillation
Masaki Hashizume, Sou Yamamoto, Hiroyuki Yotsuyanagi, Takeomi
Tamesada - The Univ. of Tokushima, Japan
9:50-12:00
1B
Delay Fault & Memory Test
Chair: Xinghao Chen, IBM, USA
1B.1
Defining appropriate SRAM resistive defects and their simulation
stimuli
A.J. van de Goor, J.E. simonse - Delft Univ. of Technology, The
Netherlands
1B.2
Vector-Based Functional Fault Models for Delay Faults
Irith Pomeranz and Sudhakar M. Reddy - Univ. of Iowa, U.S.A.
1B.3
Easily Path Delay Fault Testable Non - Restoring Cellular Array
Dividers
G. Sidiropoulos, H.T. Vergos & D. Nikolos - Univ. of Patras, Greece
1B.4
March Tests for Word-Oriented Two-Port Memories
Said Hamdioui, A.J. van de Goor - Delft Univ. of Technology, The
Netherlands
12:00-13:00
Lunch
13:00-15:00
2A
ATPG Related Approaches (II)
Chair: Sreejit Chakravarty, Intel, USA
2A.1
An Analysis of Efficiency of Test Generation Algorithms for
Combinational Circuits
Shiyi Xu and Tukwasibwe Justaf Frank - Shanghai University, China
2A.2
The Research and Realization of High Speed Test Generation Method
for Upper Large Scale Combination Circuit
Zeng Zhide - Changsha Institute of Technology, China
2A.3
Pattern Sensitivity: A Property to Guide Test Generation for
Combinational Circuits
Irith Pomeranz and Sudhakar M. Reddy - Univ. of Iowa, U.S.A.
2A.4
An Accurate Logic Threshold Voltages Determination Model for
CMOS Gates to Facilitate Test Generation and Fault Simulation
Jing-Jou Tang - Nan-Tai Institute of Technology, Taiwan
Kuen-Jon Lee - National Cheng-Kung Univ., Taiwan
13:00-15:00
2B
BIST Related Approaches
Chair: Yuejian Wu, Nortel Semiconductor, Canada
2B.1
Circuit Partitioning for Low Power BIST Design with Minimized
Peak Power Consumption
Patrick Girard, Lo?s, Guiller, Christian Landrault, Serge
Pravossoudovitch - Universit?Montpellier, France
2B.2
A Novel BIST TPG Method for Interconnect Testing Using the IEEE
1149.1 STD
W. Feng, F.J. Meyer and F. Lombardi - Northeastern University,
U.S.A.
2B.3
Test Scheduling with Loop Folding and Its Application to Test
Configurations with Accumulators
Albrecht P. Stroele and Frank Mayer - University of Karlsruhe,
Germany
2B.4
A Polynomial-Time Algorithm for Power Constrained Testing of Core
Based Systems
C.P. Ravikumar, Ashutosh Verma, and Gaurav Chandra - Indian
Institute of Technology, India
2B.5
Accelerating Test Data Processing
Serge Demidenko - Massey University, New Zealand
Kenneth Lever - University of South Australia, Australia
15:00-15:20
Coffee Break
15:20-17:30
3A
Test Generation, Diagnosis & Verification
Chair: Hiromi Hiraishi, Kyoto Sangyo University, Japan
3A.1
Procedure to Overcome the Byzantine General's Problem for Bridging
Faults in CMOS Circuits
Arabi Keshk - Osaka Univ., Japan
Yukiya Miura - Tokyo Metropolitan Univ., Japan
Kozo Kinoshita - Osaka Univ., Japan
3A.2
A Novel Fault-Detection Technique For The Parallel Multipliers And
Dividers
Chanyutt Arjhan and Raghvendra G. Deshmukh - Florida Institute of
Technology, U.S.A.
3A.3
A Fault Partitioning Method For Large Scale Parallel Test Generation
Zeng Zhide, Liu Peng-xia - National Univ. of Defense Technology,
China
15:20-17:30
3B
IDDQ Test
Chair: Dajin Wang, University of Montclair, USA
3B.1
Fault Simulation Techniques to Reduce IDDQ Measurement Vectors
for Sequential Circuits
Yoshinobu Higami - Ehime Univ., Japan
Kewal K. Saluja - Univ. of Wisconsin, U.S.A.
Yuzo Takamatsu - Ehime Univ., Japan
Kozo Kinoshita - Osaka Univ., Japan
3B.2
On An Effective Selection of IDDQ Measurement Vectors for
Sequential Circuits
Hideyuki Ichihara - Osaka Univ., Japan
Seiji Kajihara - Kyushu Institute of Technology, Japan
Kozo Kinoshita - Osaka Univ., Japan
3B.3
Scan Chain Diagnosis Using IDDQ Current Measurement
Junichi Hirase, Naoki Shindou, Kouji Akahori - Matsushita Electric
Industrial Co., Ltd., Japan
3B.4
IDDQ Current Dependency on Test Vectors and Bridging Resistance
Arabi Keshk - Osaka Univ., Japan
Yukiya Miura - Tokyo Metropolitan Univ., Japan
Kozo Kinoshita - Osaka Univ., Japan
3B.5
A Parallel Generation System of Compact IDDQ Test Sets for Large
Combinational Circuits
Tsuyoshi Shinogi, Terumine Hayashi - Mie Univ., Japan
2nd Day - Wednesday Nov.17, 1999
1st Day; 3rd Day
8:30-10:10
4A
Sequential Circuit Test
Chair: Serge Demidenko, New Zealand
4A.1
An Effective Methodology for Mixed Scan and Reset Design Based
on Test Generation and Structure of Sequential Circuits
Hsing-Chung Liang - Van Nung Ins. of Tech., Taiwan
Chung Len Lee - National Chiao Tung Univ., Taiwan
4A.2
Genetic Algorithm Based Test Generation for Sequential Circuits
Li shen - Chinese Academy of Sciences, China
4A.3
Fault (In)Dependent Cost Estimates and Conflict-directed
Backtracking to Guide Sequential Circuit Test Generation
Mario Konijnenburg - Philips Research Lab., The Netherlands
Hans van der Linden, Ad van de Goor - Delft Univ. of Tech., The
Netherlands
4A.4
Static and Dynamic Test Sequence Compaction Methods for Acyclic
Sequential Circuits Using A Time Expansion Model
Toshinori Hosokawa - Matsushita Electric Industrial Co., Ltd.,
Japan
Tomoo Inoue - Nara Ins. of Science and Tech., Japan
Toshihiro Hiraoka - Matsushita Electric Industrial Co., Ltd., Japan
Hideo Fujiwara - Nara Ins. of Science and Technology, Japan
8:30-10:10
4B
Fault-tolerant & Diagnosis
Chair: Xiaozhong Yang, Harbin Institute of Technology, China
4B.1
Activation Function Manipulation for Fault Tolerant Feedforward
Neural Networks
Yasuyuki Taniguchi, Naotake Kamiura, Yutaka Hata and Nobuyuki
Matsui - Himeji Institute of Technology, Japan
4B.2
Fault-tolerant Analysis of Feedback Neural Networks with Threshold
Neurons
Tao Zhang, Dongcheng Hu, shiyuan Yang - Tsinghua Univ., China
4B.3
Fault-Tolerant Strategies and Their Design Methods for Application
Software
Gao Jianhua, Shao Shihuang - China Textile Univ., China
4B.4
Test By Distributed Monitoring
Peng Cheng-Lian, Wu Bai-Feng, Sun xiao-Guang, Fudan Univ.,
China
10:10-10:30
Coffee Break
10:30-11:40
5A
Analog Circuits Test
Chair: Chung-Len Lee, National Chiao Tung University, Taiwan
5A.1
Optimized Statistical Analog Fault Simulation
Abdelhakim Khouas, Mohamed Dessouky and Anne Derieux -
Universit?Pierre, France
5A.2
Analog Metrology and Stimulus Selection in a Noisy Environment
Chauchin Su, Yue-Tsang Chen - National Central Univ., Taiwan
5A.3
Efficient Test Set Design for Analog and Mixed-Signal Circuits and
Systems
Sam Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg,
and Mani Soma - Univ. of Washington, U.S.A
10:30-11:40
5B
Special Session - Railway Signaling Software Testing
Chair: Yinghua Min, ICT of China, China
5B.1
Railway Signaling Safety-critical Software Testing Based on
Dynamic Decision Table
Fangmei Wu, Meng Li - Shanghai Tiedao University, China
5B.2
A Novel Testing Approach for Safety-critical Software
Zhongwei Xu, Fangmei Wu - Shanghai Tiedao University, China
5B.3
How to Design an Environment Simulator for Safety Critical
Software Testing
Haiying Tu, Fangmei Wu - Shanghai Tiedao University, China
11:45-18:30
Tour (Lunch)
18:30-20:30
Banquet
3rd Day - Thursday Nov. 18, 1999
1st Day; 2nd Day
8:30-10:10
6A
DFT
Chair: Kiyoshi, Furuya, Chuo University, Japan
6A.1
New DFT Techniques of Non-Scan Sequential Circuits with
Complete Fault Efficiency
Debesh Kumar Das - Jadavpur Univ., India
Satoshi Ohtake, Hideo Fujiwara - Nara Institute of Science and
Technology, Japan
6A.2
Identification of Redundant Crosspoint Faults in Sequential PLAs
with Fault-Free Hardware Reset
Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi and Koji
Yamazaki - Meiji Univ., Japan
6A.3
An Embedded Core DFT Scheme to Obtain Highly Compressed Test
Sets
Abhijit Jas, Kartik Mohanram and Nur A. Touba - The University of
Texas at Austin, U.S.A.
8:30-10:10
6B
Software Test & Verification
Chair: Kuen-Jong Lee, National Cheng Kung University, Taiwan
6B.1
Scenario based integration testing for Object-Oriented Software
Development
Youngchul Kim, C. Robert Carlson - Illinois Institute of
Technology, U.S.A.
Satoshi Ohtake, Hideo Fujiwara - Nara Institute of Science and
Technology, Japan
6B.2
An Approach to Testing the Nonexistence of Initial State in Z
Specifications
Miao Huaikou, Gao Xiaolei, Liu Ling - Shanghai Univ., China
6B.3
Generating Test Cases for Real-Time Software By Time Petri Nets
Model
Iao Ho & Jin-Cherng Lin - Tatung Institute of Technology, Taiwan
6B.4
Defect Level Prediction Using Multi-Model Fault Coverage
Shyue-Kung Lu and Cheng-Wen Wu - Fu Jen Catholic Univ.,
Taiwan
10:10-10:30
Coffee Break
10:30-12:00
Panel 1
Chair: Sudhakar.M.Reddy, University of Iowa, USA
Panelists:
Xinghao Chen
A.J.van de Goor
Chau Chin Su
T.W.Williams
In Nanometer Tech., How to Testing
10:30-12:00
Panel 2
Chair: Yashiwant K.Malaiya, Colorado State University
Panelists:
Yinghua Min
Chantal Robach
Difference and Unity between Hardware and Software Testing
12:00-13:00
Lunch
13:00-14:30
7A
Scan & Boundary Scan
Chair: T.W.Williams, Synopsys Inc. USA
7A.1
A High-Level Synthesis Approach to Partial Scan Design Based on
Acyclic Structure
Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara - Nara Institute of
Science and Technology, Japan
7A.2
An Input Control Technique for Power Reduction in Scan Circuits
During Test Application
Tsung-Chu Huang, Kuen-Jong Lee - National Cheng-Kung Univ.,
Taiwan
7A.3
A Simplified Method for Testing the IBM Pipeline Partial-Scan
Microprocessor
Xinghao Chen, Tom Snethen, Joe Swenton - IBM Endicott, U.S.A.
Ron Walther - IBM Austin, U.S.A
7A.4
A New Algorithm for Retiming-Based Partial Scan
Zulan Huang, Yizheng Ye, Zhigang Mao - Harbin Institute of
Technology, China
13:00-14:30
7B
Special Session - Beam Testing in Japan (I)
Chair: Hiromu Fujioka, Osaka University, Japan
7B.1
Intelligent EB Test System for Automatic VLSI Fault Tracing
Katsuyoshi Miura, Koji Nakamae and Hiromu Fujioka - Osaka
Univ., Japan
7B.2
Multiple Fault Diagnosis in Logic Circuits using EB Tester and
Multiple/Single Fault Simulators
Hiroshi Takahashi, Kwame Osei Boateng - Ehime Univ., Japan
Nobuhiro Yanagida - Kaminomoto Corporation, Japan
Yuzo Takamatsu - Ehime Univ., Japan
7B.3
Practical Application of Automated Fault Diagnosis for Stuck-at,
Bridging, and Measurement Condition Dependent Faults in Fully
Scanned Sequential Circuits
Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro
Toyota, Kiyokazu Nishi, and Akira Motohara - Matsushita Electric
Industrial Co., Ltd., Japan
14:30-14:50
Coffee Break
14:50-17:00
8A
FPGA Test
Chair: Hideo Fujiwara, Nara Institute of Science & Technology, Japan
8A.1
Minimizing the Number of Programming Steps for Diagnosis of
Interconnect Faults in FPGAs
Yinlei Yu, Jian Xu and Wei Kang Huang - Fudan Univ., China
Fabrizio Lombardi - Northeastern Univ., U.S.A.
8A.2
Minimizing the number of Test Configurations for different FPGA
Families
M. Renovell, J.M. Portal - Montpellier Cedex France
J. Figueras - UPC Diagonal, Barcelona Spain
Y. Zorian - Logic Vision Inc., U.S.A
8A.3
Testing the Logic Cells and Interconnect Resources for FPGAs
Abderrahim Doumar, Hideo Ito- Chiba Univ., Japan
8A.4
Iddq Testing of Input/Output Resources of SRAM-based FPGAs
L. Zhao, D.M.H. Walker - Texas A&M Univ., U.S.A.
F. Lombardi -Northeastern Univ., U.S.A
14:50-17:00
8B
Special Session - Beam Testing in Japan (II)
Chair: Kiyoshi Nikawa, NEC, Japan
8B.1
High Resolution CD-SEM System
Yoichi Ose, Makoto Ezumi and Hideo Todokoro - Hitachi, Japan
8B.2
Investigation of Ga Contamination due to Analysis by Dual Beam
FIB
T. Sakata - JEOL Ltd., Japan
T. Ogiwara - Japan Energy Analytical Research Center Co. Ltd.,
Japan
T. Sekine - JEOL Ltd., Japan
8B.3
Failure Analysis Case Studies Using the IR-OBIRCH (infrared optical
beam induced resistance change) Method
Kiyoshi Nikawa - NEC Corporation, Japan
Shoji Inoue - T.D.I. Co. Ltd., Japan
Kazuyuki Morimoto, shinya Sone - Naito Densei Kogyo, Co., Ltd.,
Japan
|