| IEEE Asian Test Symposium > |
7th Asian Test Symposium, ATS'98
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ATS'98
CALL FOR PAPERS
The Seventh Asian Test Symposium
December 2 - 4, 1998, Singapore
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Sponsored by
The IEEE Computer Society Test Technology Technical Committee
Computer Chapter of IEEE Singapore Section
Singapore Polytechnic
In Co-Operation with
National University of Singapore
Nanyang Technological University
SCOPE
The Asian Test Symposium provides an annual international forum for
specialists from all over the world, especially from Asia, to present and
discuss various aspects of system, board, and component testing with
design, manufacturing and field considerations in mind. Topics of interest
include, but are not limited to:
- Automatic Test Generation/Fault Simulation - Iddq Test
- Synthesis for Testability / Design for Test - Economics
of Test
- Built-In Self-Test/On-Line Testing -
Mixed Signal Test
- Fault Modelling & Diagnosis -
Electron-Beam Testing
- Simulation and Design Verification -
Failure Analysis
- Software Testing / Software Design for Test
SUBMISSIONS
Original technical papers on the above topics are invited. The submission
should not exceed 20 double-spaced pages including figures, and should
include a 50-word abstract and list of 4 to 5 keywords. Authors should
include the complete address, phone/fax numbers and e-mail address, and
designate a contact person and a presenter. The Program Committee also
welcome proposals for panels and special topic sessions. Please submit by
mail five copies of the complete manuscript by April 1, 1998 to:
Mr. Weng-Yew Wong, ATS'98 Secretary
EC Department, Singapore Polytechnic
500 Dover Road, Singapore 139651
Tel. +65 7721473, Fax. +65 7721974, E-mail wongwy(at)sp.ac.sg
The submissions will be considered evidence that upon acceptance the
author(s) will prepare the final manuscript in time for inclusion in the
proceedings and will present the paper at the Symposium.
SYMPOSIUM TIMETABLE
Submission deadline: April 1, 1998
Notification of acceptance: June 15, 1998
Camera-ready copy: August 1, 1998
For more information, please E-mail to ats98(at)sp.ac.sg
web-page : http://www.sp.ac.sg/ec1/ats98.htm.
ABOUT SINGAPORE
Singapore is a vibrant modern city-state of 3 million people and one of
Asia's four economic dragons. Situated at the southern tip of Malaysia and
in the heart of South East Asia, Singapore's geographical location has
helped her become the regional centre for trade, banking, tourism and
communications, with the world's busiest port and an
internationally-acclaimed airport which is consistently voted the world's
best. To top it all, Singapore has conference facilities that rank amongst
the finest in the world.
Singapore is a place where East meets West. Here you will find Chinese,
Malays, Indians and Eurasians living harmoniously together. English is
spoken everywhere and is the common business language of all.
Singapore has a pleasant, warm climate all year round, with temperatures
ranging from 28(superscript: o)C in the day to 23(superscript: o)C by
night. There is a rainy season from November to January. However, showers
seldom last long and they provide a cool respite.
Few places on earth promise such a delight for the palate, with gourmet
cuisine ranging from Chinese, Malay and Indian to Mexican, Japanese and
Italian. Shopping in Singapore is also about variety, quality, value for
money and excellent service. From the latest in electronics, traditional
crafts, European high fashion and traditional Asian wares to computer
software, you will find it all here in Singapore.
Theme parks, nature reserves and beach resorts are just some of Singapore's
attractions that bring visitors from around the world. Singapore's unique
central position in the South East Asian region and excellent transport
infrastructure also provides quick and easy access to idyllic tropical
retreats in Malaysia and Indonesia. Singapore is the tourism hub for tours
and cruises around the region.
For more information on Singapore, please refer to the Singapore Tourist
Promotion Board Web Page at http://www.asia-online.com.sg/sog/stpb.html
Steering Committee
Yong-Khim Swee
Texas Instruments Singapore
Dave Chong Tad-Weng
Singapore Polytechnic
Daniel Chan
National University of Singapore
Meng-Hwa Er
Nanyang Technological University, Singapore
Organising Committee
General Chairs
Yinghua Min
ICT, Chinese Academy of Sciences
min(at)mimi.cnc.ac.cn
Lee-Yee Lau
Singapore Polytechnic
lylau(at)sp.ac.sg
Program Chairs
Serge Demidenko
Singapore Polytechnic
serge.d(at)sp.ac.sg
Kiyoshi Furuya
Chuo University, Japan
furuya(at)ise.chuo-u.ac.jp
Finance Chair
Sudhir Kumar Jhajharia
Singapore Polytechnic
Sudhir.J(at)sp.ac.sg
Publicity Chair
Wilson Tan
Texas Instruments Singapore
tanw(at)msg.ti.com
Publications Chair
Hua-Swee Wang
Singapore Polytechnic
huaswee(at)sp.ac.sg
Registration Chair
Lee-Ngo Low, Cassandra
Singapore Polytechnic
LowLN(at)sp.ac.sg
Local Arrangement Chair
Teck-Bee Tan-Tay
Singapore Polytechnic
Bee(at)sp.ac.sg
Secretary
Weng-Yew Wong
Singapore Polytechnic
wongwy(at)sp.ac.sg
Industry Liaison
Jagadish C. V.
DVS Technology Singapore
dvsmgt(at)pacific.net.sg
Ex Officio
Asian Test Subcommittee Chair
Kozo Kinoshita
kozo(at)ap.eng.osaka-u.ac.jp
International Liaison
Australia/N.Zealand Liaison
Tharam S. Dillon
La Trobe University, Australia
tharam(at)cs.latrobe.edu.au
Canada Liaison
Andre Ivanov
University of British Columbia
ivanov(at)ee.ubc.ca
Europe Liaison
Bernard COURTOIS
TIMA Laboratory
Bernard.Courtois(at)imag.fr
HK/Far East Liaison
Joseph Lung
Advance Test Co, Hong Kong
jlung(at)mba1980.hbs.edu
Indonesia Liaison
Harry Sudibyo S.
University of Indonesia
elektro(at)makara.cso.ui.ac.id
Malaysia Liaison
Chooi-Choo Loke
Intel Technology Sdn Bhd
CC_Loke(at)ccm.ipn.intel.com
Halili Abd Ghani
Texas Instruments Malaysia Sdn Bhd.
hali(at)msg.ti.com
Middle East / Gulf Countries Liaison
Muhammad Khan Dhodhi
Kuwait University
mkhan(at)eng.kuniv.edu.kw
Philippines Liaison
Lito Flores
Electronic Assemblies Incorporated
EAI_eng(at)globe.com.ph
South / Central America Liaison
Marcelo Lubaszewski
Federal University of Rio Grande do Sul (UFRGS), Brazil
luba(at)iee.ufrgs.br
South Asia Regional Liaison
Syed Mahfuzul Aziz
Bangladesh University of Engineering & Technology
smaziz(at)eebuet.kaifnet.com
Taiwan Liaison
Cheng-Wen Wu
National Tsing Hua University
cww(at)ee.nthu.edu.tw
Warren Yu
Texas Instruments Taiwan
wayu(at)msg.ti.com
USA Liaison
Vishwani D. Agrawal
AT&T Bell Laboratories
va(at)research.att.com
Program Committee
V.D. Agrawal J. Abraham A.P. Ambler
R.G. Bennets M. Bushnell S.T. Chakradar
T. Chen B. Cockburn C. Dislis
H. Fujiwara A. Ginige A. van de Goor
H. Hiraishi W. K. Huang A. Ivanov
B. Kaminska H.G. Kerkhoff C. Landrault
C.L. Lee Z. Li H. Ma
M. Nikolaidis S.H. Ong V. Piuri
S.M. Reddy M. Sami J. Savir
S. Sherlekar M. Soma S.Sunter
Y. Takamatsu J. Thong P. Varma
X. Wen M. Wong C.W. Wu
S. Xu T. Yamada V. Yarmolik
M. Yoshida Tim Cheng
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ATS'98
The Seventh Asian Test Symposium
December 2 - 4, 1998
Hilton International Singapore
ADVANCE PROGRAM
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Plenary Sessions
Chair: V.Agrawal, AT&T Bell Labs, USA
Keynote Address
December 3, 8.00am - 10.00am
Keynote Speaker :Dr. T. W. Williams
Director of Research and Development, Test Technology
Synopsys, Inc.
Title : The New Frontier for Testing: Nano Meter Technologies
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Session 1A : BIST I
December 3, 10.30am - 12.30pm
Chair: C. Landrault, LIRMM, France
1.BIST Diagnostic: Simulation Models
J. Savir Ð New Jersey Institute of Technology, USA
2.Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit
F. Mayer, A. Stroele - Uni of Karlsruhe, Germany
3.Test Cycle Count Reduction in a Parallel Scan BIST Environment
B. Ayari - Duet Technologies, USA, P. Varma Ð Veritable, USA
4.A BIST Scheme for Asynchronous Logic
V. C. Alves, F. M. G. Franca, E. P. Granja - Uni Federal do Rio de Janeiro, Brazil
5.A Methodology for Minimum Area Cellular Automata Generation
P. S. Cardoso, M. Strum, J. R. de A. Amazonas, J. C. Wang - Uni de Sao Paulo, Brazil
Session 1B : HIGH LEVEL SYNTHESIS
December 3, 10.30am - 12.30pm
Chair: B.Courtois, TIMA-INPG, France
1.A High-Level Synthesis Method for Weakly Testable Data Paths
M. Inoue, T. Higashimura - NAIST, Japan, K. Noda - NEC, Japan, T. Masuzawa, H. Fiujiwara - NAIST, Japan
2.Alleviating DFT Cost Using Testability Driven HLS
M. L. Flottes, R. Pires, B. Rouzeyre - LIRMM, France
3.Reliability-Oriented HW/SW Partitioning & Verification for Critical-Application Systems
F. Vargas, E. Bezerra, L. Wulff, D.B. Junior Ð Catholic Uni Ð PUCRS, Brazil
4.An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification
H. Ichihara - Osaka Uni, S. Kajihara - Kyushu Inst of Technology, K. Kinoshita - Osaka Uni
5.Economical Importance of the Maximum Chip Area
J. Hirase - Matsushita Electric Industrial, Japan
Session 1C : DELAY TESTING
December 3, 10.30am - 12.30pm
Chair: Eran Weis, Chip Eye Technology, Israel
1.A Probabilistic Model for Path Delay Faults
C. W. Wu, C. Y. Su Ð National Tsing Hua Uni, Taiwan
2.A New Low-Cost Approach for Identifying Untestable Path Delay Faults
Z. Li, Y. Min - Inst of Computing Technology, China, R. K. Brayton - Uni of California at Berkeley, USA
3.False-Path Removal Using Delay Fault Simulation
M. A. Gharaybeh - Synopsys, USA, V. D. Agrawal - Bell Labs, Lucent Technologies, USA, M. L. Bushnell -
Rutgers Uni, USA
4.ATPG for At-Speed Robust Path Delay Fault Testing
Y. C. Hsu, S. K. Gupta - Uni of Southern California, USA
5.Delay Testing with Double Observations
H. Li, Z. Li, Y. Min - Inst of Computing Technology, China
Session 2A.1 : FAULT MODELLING & SIMULATION
December 3, 1.30pm - 3.30pm
Chair: C-L.Lee, National Chiao Tung University, Taiwan
1.On a Logical Fault Model HISGLF for Enhancing Defect Coverage
J. Sang, T. Shinogi, H. Takase, T. Hayashi - Mie Uni, Japan
2.Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation
H. Takahashi, K. O. Boateng, Y. Takamatsu - Ehime Uni, Japan
3.On the Determination of Threshold Voltages for CMOS Gates to Facilitate Test Pattern Generation and Fault
Simulation
K. J. Lee, J. J. Tang, W. Y. Duh - National Cheng-Kung Uni, Taiwan
4.Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits
S. M. Aziz - Bangladesh Uni of Engineering & Technology
Session 2A.2 : SOFTWARE TESTING
Chair: C. Messom, Dubai Polytechnic, UAE
1.Rough-Hierarchical Testing for Safety Critical Software
H. Tu, F. Wu, X. Ren - Shanghai Tiedao Uni, China
2.A Structured Testing Approach for DSP Software
E. M. La Fosse - Motorola, Singapore
Session 2B : CURRENT TESTING
December 3, 1.30pm - 3.30pm
Chair: C.V. Jagadish, DVS Technology, Singapore
1.IDDQ Testing of Submicron CMOS by Cooling
V. Szekely, M. Rencz, S. Torok - Technical Uni of Budapest, Hungary, B. Courtois - TIMA Lab, France
2.IDDQ Test Methodology & Tradeoffs For Scan/Non-Scan Designs
M. R. Patel, S. Pico, J. Fierro - Intel, USA
3.Design for Diagnosability of CMOS Circuit
X. Wen - SynTest Technologies, USA, T. Honzawa, H. Tamamoto - Akita Uni, K. K. Saluja - Uni of Wisconsin
Madison, USA, K. Kinoshita - Osaka Uni
4.IDDQ Defect Detection in Deep Submicron CMOS ICs
S. Kundu - Intel, USA
5.ATE Features for IDDQ Testing
M. G. Faust - Credence, USA
Session 2C : TEST ENGINEERING
December 3, 1.30pm - 3.30pm
Chair: W.Moorhead, Teradyne, Singapore
1.A New Technique to Ensure Quality of Test Patterns
P. C. Koo, S. L. Pang - Siemens Components, Singapore
2.Functional Testing of CPU Based Boards Using Bus Cycle Signature System
S. R. Sabapathi - Qmax Technologies, Singapore
3.Non-Intrusive Testing of High-Speed CML Circuits
V. Devdas, A. Ivanov - Uni of British Columbia, Canada
4.Testing of Line-Coupled Emissions
L. Bai, W. H. Chong - EMC Test Centre, Singapore
5.Fast Window Test Method of Hysteresis Test
T. Corpuz - Teradyne, Philippines
6.PC-Based Hard Disk Drive Bode-Plot Generator
K. W. Choo, G. Guo - Data Storage Institute, Singapore, B. M. Chen - National Uni of Singapore
Session 3A : SEQUENTIAL CIRCUIT TESTING
December 3, 4.00pm - 5.30pm
Chair: K. Hatayama, Hitachi, Japan
1.An Optimal Time Expansion Model Based on Combinational ATPG for RT Level Circuits
T. Inoue - NAIST, Japan, T. Hosokawa - Matsushita Electric Industrial, Japan, T. Mihara, H. Fujiwara - NAIST,
Japan
2.Static Test Compaction for Scan-Based Designs to Reduce Test Application Time
Pomeranz, S. M. Reddy - Uni of Iowa, USA
3.A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency
S. Ohtake, T. Masuzawa, H. Fujiwara - NAIST, Japan
4.Complete Search in Test Generation for Industrial Circuits with Improved Bus-Conflict Detection
J. Th. Van der Linden, M. H. Konijnenburg, Ad J. van de Goor - Delft Uni of Technology, The Netherlands
Session 3B : DEFECT ANALYSIS & FAULT DIAGNOSIS
December 3, 4.00pm - 5.30pm
Chair: M.Wong, HK Polytechnic University, Hong Kong
1.On Testing of Josephson Logic Circuits Consisting of RSFQ Dual-Rail Logic Gates
T. Yamada, T. Hanashima, Y. Suemori - Meiji Uni, Japan
2.Testing for Floating Gates Defects in CMOS Circuits
S. Rafiq, A. Ivanov, S. Tabatabei - Uni of British Columbia, Canada, M. Renovell - LIRMM, France
3.Advanced Test and Diagnosis for Deep Submicron ICs and Embedded Cores
S. P. Athan, J. L. Kurtz, J. Cowdery - Uni of Florida, USA
4.Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths
N. Yanagida - Kaminomoto, Japan, H. Takahashi, Y. Takamatsu - Ehime Uni, Japan
Session 3C : BOUNDARY SCAN & INTERCONNECT TESTING
December 3, 4.00pm - 5.30pm
Chair: S. Yano, Kochi University of Technology, Japan
1.BIST TPG for Combinational Cluster Interconnect Testing at Board Level
C. H. Chiang, S. K. Gupta - Uni of Southern California, USA
2.Fault Detection in a Tristate System Environment
W. Feng, W. K. Huang, F. J. Meyer, F. Lombardi - Texas A&M Uni, USA
3.Comprehensive Interconnect BIST Methodology for Virtual Socket Interface
C. Su, Y. T. Chen - National Central Uni, Taiwan
4.A DFT Methodology for High-Speed MCM Based on Boundary-Scan Techniques
Y. Sameshima, T. Fukazawa - NTT, Japan
Session 4A : FPGA TESTING
December 4, 8.15am - 9.45am
Chair: M. Jacomet, Biel School of Engineering, Switzerland
1.SRAM-Based FPGAÕs: Testing the Interconnect/Logic Interface
M. Renovell, J.M. Portal - LIRMM, France, J. Figueras - Uni Politecnica de Cataluya, Spain, Y. Zorian -
LogicVision, USA
2.Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA
N. Itazaki, F. Matsuki, Y. Matsumoto, K. Kinoshita - Osaka U, Japan
3.A Diagnosis Method for Interconnects in SRAM Based FPGAs
Y. Yu, J. Xu, W. K. Huang - Fudan Uni, China, F. Lombardi - Texas A&M Uni, USA
4.Testing and Diagnosis of Interconnect Structures in FPGAs
S. J. Wang, C. N. Huang - National Chung - Hsing Uni, Taiwan
Session 4B : ON-LINE TESTING & FAULT TOLERANCE
December 4, 8.15am - 9.45am
Chair: S.M. Azis, Bangladesh University of Engineering & Technology, Bangladesh
1.An Approach to the On-Line Testing of Operational Amplifiers
J. Velasco-Medina - TIMA/INPG, France, M. Lubaszeswski - UFRGS, Brasil, M. Nicolaidis - TIMA Lab, France
2.Self-Dual Duplication for Error Detection
VI. V. Saposhnikov, V. V. Saposhnikov - Railway Transportation State Uni, Russia, A. Dmitriev, M. Goessel -
Uni of Potsdam, Germany
3.On-Line Error Detection Schemes for a Systolic Finite-Field Inverter
Y. C. Chuang, C. W. Wu - National Tsing Hua Uni, Taiwan
4.Fault Tolerance of a Tree-Connected Multiprocessor System and Its Array-Like Layout
S. Nakano, N. Kamiura, Y. Hata - Himeji Inst of Technology, Japan
Session 4C : IDDQ TESTING
December 4, 8.15am - 9.45am
Chair: H. Tamamoto, Akita University, Japan
1.Observation Time Reduction for IDDQ Testing of Bridging Faults in Sequential Circuits
Y. Higami - Osaka Uni, Japan, K. K. Saluja - Uni of Wisconsin Madison, USA, K. Kinoshita - Osaka Uni, Japan
2.An Off-Chip Current Sensor for IDDQ Testing of CMOS ICs
Md. Altaf-Ul-Amin, Z. Md. Darus - Uni Kebangsaan, Malaysia
3.Integrated Current Sensing Device for Micro IDDQ Test
K. Nose, T. Sakurai - Uni of Tokyo, Japan
4.A High Speed IDDQ Sensor for Low-Voltage ICs
M. Hashizume, M. Ichimiya, T. TamesadaÐU of Tokushima, Japan, Y. Miura-Tokyo Metropolitan U, Japan, K.
Kinoshita - Osaka U, Japan
Session 5A : MEMORY TESTING
December 4, 10.15am - 12.30pm
Chair: W. Tan, Texas Instruments, Singapore
1.Power Analysis of DRAMs
J. Vollrath, M. Huebl, E. Stahl - Siemens AG, Germany
2.Consequences of Port Restrictions on Testing Address Decoder Faults in Two-Port Memories
S. Hamdioui, A. J. van de Goor - Delft Uni of Technology, The Netherlands
3.March LA: A Test for All Linked Memory Faults
J. van de Goor, G. N. Gaydadjiev - Delft Uni of Technology, The Netherlands, V. N. Yarmolik, V. G. Mikitjuk
State Uni of Informatics & Radioelectronics, Belarus
4.Dynamic Power Supply Current Testing of CMOS SRAMs
J. Liu - Fujitsu, USA, R. Z. Makki - Uni of North Carolina at Charlotte, USA, A. Kayssi - American Uni of
Beirut, Lebanon
5.March PS(23N) Test for DRAM Pattern-Sensitive Faults
V. Yarmolik, Yu. Klimets - State Uni of Informatics & Radioelectronics, Belarus, S. Demidenko - Singapore Poly,
Singapore
Session 5B : ANALOG & MIXED-SIGNAL TEST
December 4, 10.15am - 12.30pm
Chair: B Kaminska, OPMAXX, USA
1.Dynamic Test Set Generation for Analog Circuits and Systems
Sam Huynh, S. Kim, M. Soma, J. Zhang - Uni of Washington, USA
2.DC Nonlinear Circuit Fault Simulation With Large Change Sensitivity
M. Wong, M. Worsman - Hong Kong Polytechnic Uni, HK
3.BISTing Switched-Current Circuits
M. Renovell, F. Azais, J. C. Bodin, Y. Bertrand - LIRMM, France
4.Analog Module Metrology Using MNABST-1 P1149.4 Test Chip
Y. T. Chen, C. Su - National Central Uni, Taiwan
5.A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs)
F. Azais - LIRMM, France, A. Ivanov - Uni of British Columbia, Canada, M. Renovell, Y. Bertrand - LIRMM,
France
6.Theory and Application of Multiple Attractor Cellular Automata For Fault Diagnosis
K. Paul, A. Roy, P. K. Nandi, B. N. Roy, M. D. Purkayastha, S. Chattopadhyay, P. P. Chaudhuri - Bengal
Engineering College, India
Session 5C : DESIGN VERIFICATION
December 4, 10.15am - 12.30pm
Chair: Y. Iguchi, Yukihiro, Meiji University, Japan
1.Formal Design Techniques - Theory and Engineering Reality
C. Dislis, G. Musgrave, R. B. Hughes - Abstract Design Automation, UK
2.Verification of Asynchronous Circuit with Bounded Inertial Gate Delays
G. Jie, Eddie Wong - Nanyang Technological Uni, Singapore
3.Verification Pattern Generation for Core-Based Design Using Port Order Fault Model
S.-W. Tung - Industrial Technology Research Institute, Taiwan, J.-Y. Jou - National Chiao Tung Uni, Taiwan
4.Application of Real-Time Temporal Logic to Design Fault Detection in Responsive Communication Protocols
S. Nagano, H. Fujita, Y. Kakuda, T. Kiku
5.Design and Simulation of a RISC-Based 32-Bit Embedded On-Board Computer
Z. Guo, Li He, S. Guo, D. Wong - Beijing Inst of Control Engineering, China
6.Improving Design Robustness With the Aid of Simulation and Statistical Techniques
S. Mozar - Singapore Poly, Singapore, P. Hodgson - Deakin Uni, Australia
Session 6A : BIST II
December 4, 1.30pm - 3.30pm
Chair: M. Lubaszewski, University of Porto Alegre, Brazil
1.A Ring Architecture Strategy for BIST Test Pattern Generation
C. Fagot, O. Gascuel, P. Girard, C. Landrault - LIRMM, France
2.Exploiting BIST Approach For Two-Pattern Testing
X. Li, Paul Cheung - Uni of Hong Kong, HK
3.Low Power Built-In Self-Test
C. P. Ravikumar - Indian Institute of Technology, India, N. S. Prasad - Centre for Development of Telematics,
India
4.A BIST structure to Test Delay Faults in a Scan Environment
P. Girard, C. Landrault, V. Moreda, S. Pravossoudovitch, A. Virazel - LIRMM, France
5.An Examination of PRPG Selection Approaches for Large, Industrial VLSI Designs
Bayraktaroglu - Uni of California at San Diego, USA, K. Udawatta - Intel, USA, A. Orailoglu - Uni of California at
San Diego, USA
Session 6B : SEQUENTIAL CIRCUIT TESTING
December 4, 1.30pm - 3.30pm
Chair: H.Fujiwara, Nara Institute of Science & Technology, Japan
1.Test Generation for Synchronous Sequential Circuits Reduce Storage Requirements
Pomeranz, S. M. Reddy - Uni of Iowa, USA
2.Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits
M. S. Hsiao - Rutgers Uni, USA, S. T. Chakradhar - NEC, USA
3.Vector Restoration Using Accelerated Validation and Refinement
S. K. Bommu, K. B. Doreswamy, S. T. Chakradhar - NEC, USA
4.On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits
R. Guo, I. Pomeranz, S. M. Reddy - Uni of Iowa, USA
5.Synthesis of Sequential Circuits with Clock Control to Improve Testability
K. L. Einspar - Concordia College, USA, S. K. Mehta, S. C. Seth - Uni of Nebraska-Lincoln, USA
Session 6C : TEST PROGRAM GENERATION
December 4, 1.30pm - 3.30pm
Chair: Q-F. Chen, Beijing Institute of Automatic Test Technology, China
1.A Test Pattern Generation Algorithm Exploiting Behavioral Information
S. Chusano, F. Corno, P. Prinetto - Politecnico di Torino, Italy
2.A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination
Pomeranz - Uni of Iowa, USA, W. K. Fuchs - Purdue Uni, USA
3.Special ATPG to Correlate Test Patterns for Low-Overhead Mixed-Mode BIST
M. Karkala, N. A. Touba - Uni of Texas at Austin, USA, H.-J. Wunderlich - Uni of Stuttgart, Germany
4.Test Pattern Generation for Column Compression Multiplier
P. Zheng, Z. Mao, Y. Ye and Y. Deng - Harbin Inst of Technology, China
5.Counter Random Testing
S. Xu - Shanghai Uni, China
Panel Discussions
December 4, 4.00pm - 5.30pm
Panel 1 :
Title: Microsystem Testing: Challenge or Common Knowledge ?
Organizer: H. Kerkhoff, MESA - University of Twente, The Netherlands
Panel 2 :
Title: Testing Embedded Memories: Is BIST the Ultimate Solution?
Organizer: C.W. Wu, National Tsing Hua University, Taiwan
Post Symposium Social Function
December 4, 7.00pm - 10.00pm
Optional Social function (Advanced Booking only)
Asia-Pacific Brewery visit cum dinner
The program includes an AV presentation on Asia Pacific Brewery and its activities. This is followed by a tour of the
Brew House and then a seafood dinner at the Tiger Tavern with free flow of beer straight from the Brew House.
Transportation will be provided to and from Hilton Hotel. Cost is US$30 per person.
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