IEEE Asian Test Symposium > |
6th Asian Test Symposium, ATS'97
CALL FOR PAPERS The Sixth Asian Test Symposium (ATS'97) November 17-19, 1997 Akita Castle Hotel, Akita, Japan Sponsored by the IEEE Computer Society Test Technology Technical Committee (TTTC) In Cooperation with: Technical Group on Fault Tolerant Systems, IEICE Special Interest Group on Design Automation, IPS Japan Japan Society for the Promotion of Science, 132nd Committee (Electron and Ion Beam Science and Technology) Mining College, Akita University SCOPE The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the world, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. Topics of interest include, but are not limited to: - Automatic Test Generation / Fault Simulation - Synthesis for Testability / Design for Testability - Built-in Self-Test / On-line Testing - Iddq Test - Fault Modeling & Diagnosis - Mixed-Signal Test - Design Verification - Electron-Beam Testing - Economics of Test - Software Testing / Software Design for Testing SUBMISSIONS Original technical papers on the above topics are invited. These should not exceed 20 double-spaced pages including figures, and should include a 50-word abstract and a list of 4 to 5 keywords. Authors should include the complete address, phone/fax numbers and e-mail address, and designate a contact person and a presenter. The Program Committee also welcomes proposals for panels and special topics sessions. Please submit five copies of complete manuscript to the Program Chair by April 15, 1997. The submission will be considered evidence that upon acceptance the author(s) will prepare the final manuscript in time for inclusion in the proceedings and will present the paper at the Symposium. Prof. Teruhiko Yamada Department of Computer Science, Meiji University 1-1-1 Higashimita, Tama-Ku, Kawasaki 214, Japan Fax: +81-44-934-7912, Tel: +81-44-934-7452 E-mail: yamada(at)cs.meiji.ac.jp SYMPOSIUM TIMETABLE Submission deadline : April 15, 1997 Notification of acceptance: June 30, 1997 Camera-ready Copies: August 5, 1997 Symposium: November 17-19, 1997 ORGANIZING COMMITTEE Symposium Chair: Yuzo Takamatsu Ehime University takamatsu(at)cs.ehime-u.ac.jp Program Chair: Teruhiko Yamada Meiji University yamada(at)cs.meiji.ac.jp Finance Chair: Kiyoshi Furuya Chuo University furuya(at)ise.chuo-u.ac.jp Publicity Chair: Hideo Fujiwara Nara Institute of Science and Technology fujiwara(at)is.naist.jp Publications Chair: Hirome Hiraishi Kyoto Sangyo University hiraishi(at)cc.kyoto-su.ac.jp Registration Chair: Masahide Takada NEC Corporation mtakada(at)lsi.tmg.nec.co.jp Local Arrangement Chair: Hideo Tamamoto Akita University tamamoto(at)ie.akita-u.ac.jp Secretary: Hiroshi Takahashi Ehime University takahashi(at)cs.ehime-u.ac.jp US Liaison: Vishwani D. Agrawal AT & T Bell Laboratories va(at)research.att.com Europe Liaison: Bernard Courtois INPG/TIME courtois(at)archi.imag.fr Ex Office: Group Chair, Asian Activities TTTC, IEEE Computer Society Kozo Kinoshita Osaka University kozo(at)ap.eng.osaka-u.ac.jp Program Committee: A.P. Ambler, Brunel University, UK S.T. Chakradhar, NEC USA, USA P.P. Chaudhuri, Indian Institute of Technology, India S. Demidenko, Singapore Polytechnic, Republic of Singapore H. Fujioka, Osaka University, Japan Y. Furukawa, Advantest Corporation, Japan A. J. van de Goor, Delft University of Technology, The Netherlands K. Hatayama, Hitachi, Ltd., Japan M. Hashizume, University of Tokushima, Japan M. Hayashi, Mie University, Japan F. Hirose, Fujitsu Labs. Ltd., Japan M. Ishikawa, Toshiba Corporation, Japan H. Ito, Chiba University, Japan A. Ivanov, University of British Columbia, Canada K. Iwasaki, Tokyo Metropolitan University, Japan B. Kaminska, Ecole Polytechnique de Montreal, Canada T. Kikuno, Osaka University, Japan Y. Koseko, Mitsubishi Electric Corporation, Japan C.L. Lee, National Chiao Tung University, Taiwan T. Manmoto, IBM Japan, Ltd., Japan Y. Min, Academia Sinica, China A. Motohara, Matsushita Elec. Industrial Co., Ltd., Japan M. Nicolaidis, TIMA/INPG, France I. Pomeranz, University of Iowa, USA E. Prochaska, Fachhochschule Heilbronn, Germany J. Rajski, Mentor Graphics Corp., USA A. Rubio, Universitat Politecnica de Catalunya, Spain K.K. Saluja, University of Wisconsin-Madison, USA T. Sasao, Kyushu Institute of Technology, Japan J. Savir, IBM Somerset, USA S.C. Seth, University of Nebraska, USA S.D. Sherlekar, ASIC Technologies Pvt. Ltd., India N. Suenaga, Oki Elec. Industry Co., Ltd., Japan N. Takagi, Nagoya University, Japan M. Teramoto, NTT LSI Laboratories, Japan M. Tsunoyama, Niigata Institute of Technolog, Japan P. Varma, Crosscheck Technolgy, USA X. Wen, Akita University, Japan C.W. Wu, National Tsing Hua University, Taiwan S. Xu, Shanghai University of Science and Technology, China T. Yokohira, Okayama University, Japan T. Yoneda, Tokyo Institute of Technology, Japan M. Yoshida, NEC Corperation, Japan Y. Zorian, AT&T Bell Laboratories, USA ------------------------------------------------------------------- TECHNICAL PROGRAM ------------------------------- Monday November 17th, 1997 ------------------------------- 8:30 - 9:30 Plenary Session ------------------------------- Welcome Message: Y. Takamatsu, General Chair Keynote Address: Embedded Test & Measurement is Critical for Deep Submicron Technology Vinod K. Agarwal, Logic Vision, U.S.A. Program Introduction: T. Yamada, Program Chair ------------------------------- 9:30 - 10:00 Coffee Break ------------------------------- 10:00 - 12:00 1A Test Generation I ------------------------------- Chair: J. Savir - New Jersey Inst. of Technology, U.S.A. 1A.1 On the Compaction of Test Sets Produced by Genetic Optimization I. Pomeranz, S. M. Reddy - Univ. of Iowa, U.S.A. 1A.2 On the Adders with Minimum Tests S. Kajihara, T. Sasao - Kyushu Inst. of Technology, Japan 1A.3 Test Generation for Stuck-On Faults in BDD-Based Pass-Transistor Logic SPL T. Shinogi, T. Hayashi - Mie Univ., Japan, K. Taki - Kobe Univ., Japan 1A.4 An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits N. Itazaki, Y. Idomoto, K. Kinoshita - Osaka Univ., Japan ------------------------------- 10:00 - 12:00 1B DFT I ------------------------------- Chair: S. K. Jhajharia - Singapore Polytechnic, Singapore 1B.1 Guaranteeing Testability in Re-Encoding for Low Power S. Chiusano, F. Corno, P. Prinetto, M. Rebaudengo, M. S. Reorda - Politecnico di Torino, Italy 1B.2 Automatic Testability Analysis of Boards and MCMs at Chip Level M. Perbost , L. Lelan - Dassault Electronique, France, C. Landrault - LIRMM, France 1B.3 Design of C-Testable Multipliers Based on the Modified Booth Algorithm K. O. Boateng, H. Takahashi, Y. Takamatsu - Ehime Univ., Japan 1B.4 Testability Prediction for Full Scan Sequential Circuits Using Neural Networks G. P. Dias - Fudan Univ., China, S. Xu, P. Waiganjo - Shanghai Univ. of Science and Technology, China ------------------------------- 12:00 - 13:00 Lunch ------------------------------- 13:00 - 15:00 2A Test Generation II ------------------------------- Chair: B. Kaminska - OPMAXX, U.S.A. 2A.1 A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits F. Corno, P. Prinetto, M. Rebaudengo, M. S. Reorda, G. Squillero - Politecnico di Torino, Italy 2A.2 Sequential Test Generation Based on Circuit Pseudo-Transformation S. Ohtake, T. Inoue, H. Fujiwara - Nara Inst. of Science and Technology, Japan 2A.3 Exploiting Logic Simulation to Improve Simulation-Based Sequential ATPG F. Corno, P. Prinetto, M. Rebaudengo, M. S. Reorda, M. Violante - Politecnico di Torino, Italy 2A.4 TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits I. Pomeranz, S. M. Reddy - Univ. of Iowa, U.S.A. ------------------------------- 13:00 - 15:00 2B Fault Tolerance ------------------------------- Chair: N. Kanekawa - Hitachi, Japan 2B.1 Design and Implementation of Strongly Code-Disjoint CMOS Built-In Intermediate Voltage Sensor for Totally Self-Checking Circuits J. C. W. Pang, M. W. T. Wong, Y. S. Lee - Hong Kong Polytechnic Univ., Hong Kong 2B.2 On Fault Injection Approaches for Fault Tolerance of Feedforward Neural Networks T. Ito, I. Takanami - Iwate Univ., Japan 2B.3 A Concurrent Fault-Detection Scheme for FFT Processors M.Tsunoyama - Niigata Inst. of Technology, Japan, M.Uenoyama - Uenoyama Fuel Co., Japan, T. Kabasawa - Nagaoka College of Technology, Japan 2B.4 Code-Disjoint Circuits for Parity Codes H. Hartje - Univ. of Potsdam, Germany, E. S. Sogomonyan - Russian Academy of Sciences, Russia, M. Gossel - Univ. of Potsdam, Germany ------------------------------- 15:00 - 15:25 Coffee Break ------------------------------- 15:25 - 17:30 3A Special Session I Case Studies for DFT Techniques in Japanese Industry ------------------------------- Chair & Coordinator: Masaaki Yoshida - NEC, Japan 3A.1 Testability Features of R10000 Microprocessor J. Mori - Toshiba, Japan, B. Mathew, D. Burns, Y. H. Mok - Silicon Graphics, U.S.A. 3A.2 Application of a Design for Delay Testability Approach to High Speed Logic LSIs K. Hatayama, M. Ikeda - Hitachi, Japan, M. Takakura, S. Uchiyama - Hitachi Engineering, Japan, Y. Sakamoto - Hitachi Information Technology, Japan 3A.3 An Effective Fault Simulation Method for Core Based LSIs T. Yoshida, R. Shimoda, T. Mizokawa, K. Hirayama - Matsushita, Japan 3A.4 Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs T. Ono, K. Wakui, H. Hikima, Y. Nakamura, M. Yoshida - NEC, Japan 3A.5 ATREX: Design for Testability System for Mega Gate LSIs M. Emori, J. Kumagai, K. Itaya, T. Aikyo - Fujitsu, Japan, T. Anan, J. Niimi - Fujitsu LSI Technology, Japan ------------------------------- 15:25 - 17:30 3B Test Technologies (Short presentations) ------------------------------- Chair: M. Nishihara - IBM Japan, Japan 3B.1 On Energy Efficiency of VLSI Testing C. W. Wu - National Tsing Hua Univ., Taiwan 3B.2 ProTest: A Low Cost Rapid Prototyping and Test System for ASICs and FPGAs M. Jacomet, R. Walti, L. Winzenried, J. Perez, M. Gysel - Technical Eng. School Biel, Switzerland 3B.3 Computing Stress Tests for Interconnect Defects V. Dabholkar - Motorola, U.S.A., S. Chakravarty - State Univ. of New York, U.S.A. 3B.4 Analysis of the Feasibility of Dynamic Thermal Testing in Digital Circuits J. Altet, A. Rubio - Univ. Politecnica de Catalunya, Spain, H. Tamamoto - Akita Univ., Japan 3B.5 A Test Processor Chip Implementing Multiple Seed, Multiple Polynomial Linear Feedback Shift Register Z. M. Darus - Univ. Kebangsaan, Malaysia, I. Ahmed - Univ. of Malaya, Malaysia, L. Ali - Univ. Kebangsaan, Malaysia ------------------------------- Tuesday November 18th, 1997 ------------------------------- 8:30 - 10:00 4A Special Session II Beam Testing of VLSI Circuits in Japan ------------------------------- Chair: Kiyoshi Nikawa - NEC, Japan Coordinator: Hiromu Fujioka - Osaka Univ., Japan 4A.1 Automatic EB Fault Tracing System by Successive Circuit Extraction from VLSI CAD Layout Data K. Miura, K. Nakata, K. Nakamae, H. Fujioka - Osaka Univ., Japan 4A.2 An Approach to Diagnose Logical Faults in Partially Observable Sequential Circuits K. Yamazaki, T. Yamada - Meiji Univ., Japan 4A.3 Guided-Probe Diagnosis of Macro-Cell-Designed LSI Circuits N. Kuji - NTT, Japan ------------------------------- 8:30 - 10:00 4B Mixed-Signal Test ------------------------------- Chair: C. W. Wu - National Tsing Hua Univ., Taiwan 4B.1 A Perturbation Based Fault Modeling and Simulation for Mixed-Signal Circuits N. Ben-Hamida, K. Saab, D. Marche, B. Kaminska - OPMAXX, U.S.A. 4B.2 Static Testing of ADCs Using Wavelet Transforms T. Yamaguchi - Advantest Lab., Japan 4B.3 Analog Signal Metrology for Mixed Signal ICs C. Su, Y. R. Cheng, Y. T. Chen - National Central Univ., Taiwan, S. Tenchen - Telecommunication Lab., Taiwan ------------------------------- 10:00 - 10:15 Coffee Break ------------------------------- 10:15 - 11:45 5A Special Session III Novel Beam Testing Techniques in Japan ------------------------------- Chair: Motosuke Miyoshi - Toshiba, Japan Coordinator: Hiromu Fujioka - Osaka Univ., Japan 5A.1 A New Auto-Focus Method in Critical Dimension Measurement SEM F. Komatsu, H. Motoki, M. Miyoshi - Toshiba, Japan 5A.2 Novel Optical Probing System for Quarter - mm VLSI Circuits K. Ozaki, H. Sekiguchi, S. Wakana, Y. Goto - Fujitsu Labs., Japan, Y. Umehara, J. Matsumoto - Advantest, Japan 5A.3 New Capabilities on OBIRCH Method for Fault Localization and Defect Detection K. Nikawa -NEC, Japan, S. Inoue - TDI, Japan ------------------------------- 5B Decision Diagrams and Logic Optimization 10:15 - 11:45 ------------------------------- Chair: E. Prochaska - Fachhochschule Heilbronn, Germany 5B.1 On Acceleration of Logic Circuits Optimization Using Implication Relations H. Ichihara, K. Kinoshita - Osaka Univ., Japan 5B.2 A Variable Reordering Method for Fast Optimization of Binary Decision Diagrams M. B. Song, H. Chang - Soongsil Univ., Korea 5B.3 On Decomposition of Kleene TDDs Y. Iguchi - Meiji Univ., Japan, T. Sasao, M. Matsuura - Kyushu Inst. of Technology, Japan ------------------------------- 11:45 - 19:00 Tour (Lunch) ------------------------------- 19:00 - 21:00 Banquet ------------------------------- Wednesday November 19th, 1997 ------------------------------- 8:30 - 10:00 6A FPGA Test ------------------------------- Chair: S. Xu - Shanghai Univ. of Science and Technology, China 6A.1 Testing for the Programming Circuit of LUT-Based FPGAs H. Michinishi, T. Yokohira, T. Okamoto - Okayama Univ., Japan, T. Inoue, H. Fujiwara - Nara Inst. of Science and Technology, Japan 6A.2 A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs W. K. Huang - Fudan Univ., China, F. J. Meyer, F. Lombardi - Texas A&M Univ., U.S.A. 6A.3 Test Pattern Generation and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA M. Renovell, J. M. Portal - LIRMM, France, J. Figueras - Univ. Politecnica de Catalunya, Spain, Y. Zorian - Logic Vision, U.S.A. ------------------------------- 8:30 - 10:00 6B Software Test ------------------------------- Chair: T. Yoneda - Tokyo Inst. of Technology, Japan 6B.1 Source-to-Source Instrumentation of C Based Languages: Application to the Memory Optimization of an Automatic Bank Check Reading System P. B. Pereira - Matra Systemes et Information, France, L. Heutte - Univ. de Rouen, France, J. V. Moreau - Matra Systemes et Information, France, P. Courtellemont, Y. Lecourtier - Univ. de Rouen, France 6B.2 An Algorithm for All-Du-Path Testing Coverage of Shared Memory Parallel Programs C. S. D. Yang, L. L. Pollock - Univ. of Delaware, U.S.A. 6B.3 Estimating the Number of Faults Using Simulator Based on Generalized Stochastic Petri-Net Model O. Mizuno, S. Kusumoto, T. Kikuno - Osaka Univ., Japan, Y. Takagi, K. Sakamoto - OMRON, Japan ------------------------------- 10:00 - 10:30 Coffee Break ------------------------------- 10:30 - 12:00 7A Diagnosis ---------------------------- Chair: Y. Min - Chinese Academy of Sciences, China 7A.1 On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs T. Inoue, S. Miyazaki, H. Fujiwara - Nara Inst. of Science and Technology, Japan 7A.2 Fault Diagnosis for Static CMOS Circuits W. Xiaoqing, H. Tamamoto - Akita Univ., Japan, K. K. Saluja - Univ. of Wisconsin, U.S.A., K. Kinoshita - Osaka Univ., Japan 7A.3 Fault Diagnosis of Odd-Even Sorting Networks C. W. Hu, C. L. Lee, W. C. Wu - National Chiao Tung Univ., Taiwan, J. E. Cheng - Chung-Hua Polytechnic Inst., Taiwan ------------------------------- 10:30 - 12:00 7B DFT II ------------------------------- Chair: A. Ivanov - Univ. of British Columbia, Canada 7B.1 On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers J. Savir - New Jersey Inst. of Technology, U.S.A. 7B.2 Test Compaction in a Parallel Access Scan Environment S. Bhatia, P. Varma - Duet Technologies, U.S.A. 7B.3 A Partial Scan Design Method Based on n-Fold Line-Up Structures T. Hosokawa, T. Hiraoka, M. Ohta, M. Muraoka, S. Kuninobu - Matsushita, Japan ------------------------------- 12:00 - 13:00 Lunch ------------------------------- 13:00 - 15:00 8A Delay Test ----------------------------- Chair: C. Landrault - LIRMM, France 8A.1 On the Capability of Delay Tests to Detect Bridges and Opens S. Chakravarty - State Univ. of New York, U.S.A. 8A.2 A Method of Generating Tests for Marginal Delays and Delay Faults in Combinational Circuits H. Takahashi - Ehime Univ., Japan, T. Matsunaga - NEC, Japan, K. O. Boateng, Y. Takamatsu - Ehime Univ., Japan 8A.3 Memory Efficient ATPG for Path Delay Faults W. Long - Tsinghua Univ., China, Z. Li - Chinese Academy of Sciences, China, S. Yang - Tsinghua Univ., China, Y. Min- Chinese Academy of Sciences, China 8A.4 Design of Delay-Verifiable Combinational Logic by Adding Extra Inputs X. Yu, Y. Min - Chinese Academy of Sciences, China ------------------------------- 13:00 - 15:00 8B BIST I ------------------------------- Chair: K. Iwasaki - Tokyo Metropolitan Univ., Japan 8B.1 BIST Testability Enhancement Using High Level Test Synthesis for Behavioral and Structural Designs K. Lai - Rockwell Semiconductor Systems, U.S.A., C. A. Papachristou, M. Baklashov - Case Western Reserve Univ., U.S.A. 8B.2 On Chip Weighted Random Patterns J. Savir - New Jersey Inst. of Technology, U.S.A. 8B.3 Random Pattern Testable Design with Partial Circuit Duplication H. Yokoyama, W. Xiaoqing, H. Tamamoto - Akita Univ., Japan 8B.4 Accelerated Test Points Selection Method for Scan-Based BIST M. Nakao, K. Hatayama, I. Higashi - Hitachi, Japan ------------------------------- 15:00 - 15:30 Coffee Break ------------------------------- 15:30 - 17:30 9A Current Testing ------------------------------- Chair: J. E Chen - Chung-Hua Polytechnic Inst., Taiwan 9A.1 Power Supply Current Monitoring Techniques for Testing PLLs M. Dalmia, A. Ivanov, S. Tabatabaei - Univ. of British Columbia, Canada 9A.2 Supply Current Test for Unit-to-Unit Variations of Electrical Characteristics in Gates M. Hashizume, T. Kuchii, T. Tamesada - Tokushima Univ., Japan 9A.3 IDDT Testing Y. Min, Z. Zhao, Z. Li - Chinese Academy of Sciences, China 9A.4 Built-In Current Sensor Designs Based on the Bulk-Driven Technique K. J. Lee, T. C. Huang, M. C. Huang - National Cheng-Kung Univ., Taiwan ------------------------------- 15:30 - 17:30 9B BIST II ------------------------------- Chair: T. Tada - Mitsubishi, Japan 9B.1 Test Length for Random Testing of Sequential Machines Application to RAMs R. David - Lab. d'Automatique de Grenoble, France 9B.2 Built-In Self-Test for Multi-Port RAMs Y. Wu, S. Gupta - Northern Telecom, Canada 9B.3 An Extended March Test Algorithm for Embedded Memories G. M. Park, H. Chang - Soongsil Univ., Korea 9B.4 Low Cost BIST for EDAC Circuits D. Badura - Silesian Univ. of Katowice, Poland, A. Hlawiczka - Silesian Technical Univ. of Gliwice, Poland |