| IEEE Asian Test Symposium > |
4th Asian Test Symposium, ATS'95
T H E F O U R T H A S I A N T E S T S Y M P O S I U M
=============================================================
November 23-24, 1995
Oberoi Hotel, Bangalore, India
ABOUT THE SYMPOSIUM
===================
The Asian Test Symposium provides an international forum for engineers and
researchers from all countries of the world, especially from Asia, to present
and discuss various aspects of system, board, and device testing with design,
manufacturing and field considerations in mind.
ATS'95 - The Fourth Asian Test Symposium will be held in Bangalore on
November 23-24, 1995 at Oberoi Hotel. The two-day technical program includes
paper presentations (in 2 parallel sessions) and a panel discussion on "New
Research Problems in the Emerging Test Technology". The details are given
in the attached Advance Program.
ATS'95 Symposium Chair: Sunil D. Sherlekar
Silicon Automation Systems (India) Ltd.,
3008,12th B Main, 8th Cross, HAL 2nd stage,
Bangalore 560008, INDIA
Tel: +91-80-5281229
Fax: +91-80-5284396
e-mail: sds(at)sasi.ernet.in
Program Chair: Vishwani D. Agrawal
AT&T Bell Laboratories,
600 Mountain Avenue, Rm.2C-476
Murray Hill, NJ 07974, USA
Tel: +1-908-582-4349
Fax: +1-908-582-5857
e-mail: va(at)research.att.com
----------------------------------------------------------------------------
----
ADVANCE PROGRAM (8/5/95)
Fourth Asian Test Symposium
Oberoi Hotel, Bangalore, India, November 23-24, 1995
Note: Time and day of papers may change in the final program
* Denotes 15-minute presentation. All others are 25 minutes.
THURSDAY, NOVEMBER 23, 1995
7:00AM REGISTRATION BEGINS
8:30AM - 9:00AM OPENING REMARKS
K. Kinoshita, S.D. Sherlekar and V.D. Agrawal
9:00AM - 10:20AM SESSION 1. SYSTEMS TEST
Chair: D. Nikolos, U. of Patras - Greece
1.1 Distributed Off-line Testing of Parallel Systems, O. Benkahla,
C. Aktouf and C. Robach, IMAG - France
1.2 An SBus Multi Tracer and Its Applications, H.A. Xie, K. Forward,
K.M. Adams and S. Kumar, U. of Melbourne - Australia
1.3*Exploitation of Parallelism in Group Probing for Testing
Massively Parallel Processing Systems, Y.-H. Choi and C. Kim,
Hongik U. - Korea
1.4*A Cellular Array Designed from a Multiple-Valued Decision
Diagram and Its Fault Tests, N. Kamiura, Y. Hata and K. Yamato,
Himeji Inst. of Tech. - Japan
9:00AM - 10:20AM ANALYSIS TECHNIQUES
Chair: S. Xu, Shanghai U. of Sci. Tech. - China
2.1 Boolean Process - An Analytical Approach to Circuit
Representation (II), Y. Min, Z. Zhao and Z Li, Inst. of
Computing Tech. - China
2.2 Fanout Fault Analysis for Digital Logic Circuits, J.E. Chen,
Chung-Hua Polytechnic Inst. - Taiwan, C.L. Lee, W.Z. Shen and
B. Chen, National Chiao Tung U. - Taiwan
2.3*Metastability Evaluation by Propagation Delay Distribution
Measurement, B.M. Rogina and B. Vojnovic, Ruder Boskovic Inst. -
Croatia
2.4*An Approach to Hierarchy Model Checking via Evaluating CTL
Hierarchically, Z. Zhang, Fraunhofer Inst. - Germany
10:30AM - 11:00AM TEA BREAK
11:00AM - 12:55PM SESSION 3. DIAGNOSIS
Chair: B. Courtois, TIMA - France
3.1 Transistor Leakage Fault Location with IDDQ Measurement,
W. Xiaoqing and H. Tamamoto, Akita U. - Japan, and K. Kinoshita,
Osaka U. - Japan
3.2 Enhancing Multiple Fault Diagnosis in Combinational Circuits Based
on Sensitized Paths and EB Testing, H. Takahashi, N. Yanagida and
Y. Takamatsu, Ehime U. - Japan
3.3 A Simple Technique for Locating Gate-Level Faults in Combinational
Circuits, T. Yamada and K. Yamazaki, Meiji U. - Japan, and
E.J. McCluskey, Stanford U. - USA
3.4 A Fault Location Technique and Alternative Routing in Benes Network,
N. Das and J. Dattagupta, Indian Statistical Inst. - India
11:00AM - 12:55PM SESSION 4. FAULT SIMULATION
Chair: C.L. Lee, Nat. Chiao Tung U. - Taiwan
4.1 Overhead Reduction Techniques for Hierarchical Fault Simulation,
E. Harada, NEC - Japan, and J.H. Patel, U. of Illinois - USA
4.2 On the Simulation of Multiple Stuck-at Faults using Multiple Domain
Concurrent and Comparative Simulation, K.P. Lentz, Tufts U. - USA,
E.S. Manolakos and E.W. Czeck, Northeastern U. - USA
4.3 Fast Fault Simulation for BIST Applications, C.-P. Kung and
C.-S. Lin, National Taiwan U. - Taiwan
4.4 Serial Transistor Network Modeling for Bridging Fault Simulation,
M. Renovell, P. Huc and Y. Bertrand, LIRMM - France
4.5*Hardware-Accelerated Concurrent Fault Simulation: Eventflow
Computing versus Dataflow Computing, W. Hahn, A. Hegerer and
R. Kandlbinder, U. of Passau - Germany
1:00PM - 2:00PM LUNCH
2:00PM - 4:05PM SESSION 5. MIXED-SIGNAL TEST
Chair: M.M. Hasan, IIT, Kanpur - India
5.1 A Design-for-Test Technique for Multi-Stage Analog Circuits,
M. Renovell, F. Azais and Y. Bertrand, LIRMM - France
5.2 DC Control and Observation Structures for Analog Circuits,
Y.-R. Shieh and C.-W. Wu, National Tsing Hua U. - Taiwan
5.3 A New Method for Testing Mixed Analog and Digital Circuits,
J. Rzeszut, B. Kaminska and Y. Savaria, Ecole Polytech. de
Montreal - Canada
5.4 On the Development of Power Supply Voltage Control Testing
Technique for Analog Circuits, A.K.B. A'ain, A.H. Bratt and
A.P. Dorey, Lancaster U. - UK
5.5*Tolerance DC Bands of CMOS Operational Amplifier, H. Ihs and
C. Dufaza, LIRMM - France
2:00PM - 4:05PM SESSION 6. DESIGN FOR TESTABILITY
Chair: C.-S. Lin, Nat. Taiwan U. - Taiwan
6.1 Theory and Applications of Cellular Automata for Synthesis of
Easily Testable Combinational Logic, S. Nandi and P. Palchaudhuri,
Indian Inst. of Tech. Kharagpur - India
6.2 Unified Scan Design with Scannable Memory Arrays, S. Yano, NEC
Corp. - Japan
6.3 Test Configurations to Enhance Testability of Sequential Circuits,
S. Lavabre, Y. Bertrand, M. Renovell and C. Landrault, LIRMM -
France
6.4 Test Sequence Compaction by Reduced Scan Shift and Retiming,
Y. Higami, S. Kajihara and K. Kinoshita, Osaka U. - Japan
6.5 Testable Design of Non-Scan Sequential Circuits Using Extra
Logic, D.K. Das, Jadavpur U. - India, and B.B. Bhattacharya,
Indian Statistical Inst. - India
4:30PM - 5:45PM SESSION 7. EDUCATION AND RESEARCH IN TESTING
Chair and Moderator: V.D. Agrawal, AT&T Bell Labs - USA
7.1* Training Diploma Students on ATE-Related Module, S.K. Jhajharia
and H.S. Wang, Singapore Polytechnic - Singapore
7.2 Panel: New Research Problems in the Emerging Test Technology,
Panelists: B. Courtois, TIMA - France; F. Hirose, Fujitsu -
Japan; S. Kundu, IBM - USA; C.L. Lee, Nat. Chiao
Tung U. - Taiwan; Y. Min, ICT - China;
P. Palchaudhuri, IIT Kharagpur - India.
7:00PM - 9:00PM EVENING RECEPTION
FRIDAY, NOVEMBER 24, 1995
9:00AM - 10:15AM SESSION 8. TESTABILITY MEASURES
Chair: B.B. Bhattacharya, ISI - India
8.1 A STAFAN-Like Functional Testability Measure for Register-Level
Circuits, C.P. Ravikumar, G. Saund and N. Agrawal, Indian Inst.
of Tech. Delhi - India
8.2 Testability Forecasting for Sequential Circuits, S. Xu and
G.P. Dias, Shanghai U. of Science and Tech. - China
8.3 Testability Analysis of Co-designed Systems, Y.L. Traon and
C. Robach, IMAG - France
9:00AM - 10.15AM SESSION 9. DELAY TEST - I
Chair: P. Varma, CrossCheck - USA
9.1 Generator Choices for Delay Test, J. Savir, IBM Microelectronics -
USA
9.2 Static Compaction for Two-Pattern Test Sets, I. Pomeranz and
S.M. Reddy, U. of Iowa - USA
9.3 Identification of Robust Untestable Path Delay Faults, W.C. Wu
and C.L. Lee, National Chiao Tung U. - Taiwan, and J.E. Chen,
Chung-Hua Polytechnic Inst. - Taiwan
10:15AM - 10:45AM TEA BREAK
10:45AM - 12:50PM SESSION 10. ATPG
Chair: S. Kundu, IBM - USA
10.1 An Improved Hierarchical Test Generation Technique for
Combinational Circuits with Repetitive Sub-Circuits, D.R.
Chakrabarti and A. Jain, Indian Inst. of Tech. Kanpur - India
10.2 Deterministic Test Generation for Non-Classical Faults on the
Gate Level, U. Mahlstedt, J. Alt and I. Hollenbeck, U. of
Hannover - Germany
10.3 A Parallel Sequential Test Generation System DESCARTES Based on
Real-Valued Logic Simulation, H. Date, M. Nakao and K. Hatayama,
Hitachi Research Lab. - Japan
10.4 Universal Test Complexity of Field-Programmable Gate Arrays,
T. Inoue and H. Fujiwara, NAIST - Japan, and H. Michinishi,
T. Yokohira and T. Okamoto, Okayama U. - Japan
10.5 Software Transformations for Sequential Test Generation,
A. Balakrishnan, Rutgers U. - USA, and S.T. Chakradhar, NEC - USA
10:45AM -12:50PM SESSION 11. BIST
Chair: K. Furuya, Chuo U. - Japan
11.1 Module Level Weighted Random Pattrens, J. Savir, IBM
Microelectronics - USA
11.2 A Programmable Multiple-Sequence Generator for BIST Applications,
M.L. Sheu and C.L. Lee, National Chiao Tung U. - Taiwan
11.3 An Effective BIST Scheme for Carry-Save and Carry-Propagate
Array Multipliers, D. Gizopoulos and A. Paschalis, DEMOKRITOS -
Greece, and Y. Zorian, AT&T Bell Labs - USA
11.4*Fast Computation of C-MISR Signatures, M. Franklin, Clemson U. -
USA
11.5*An Effective BIST Design for PLA, J.-Y. Jou, National Chiao
Tung U. - Taiwan
11.6*Error Masking in Compact Testing Based on the Hamming Code and
its Modifications, S. Demidenko, Singapore Polytechnic - Singapore,
A. Ivanyukovich, BelarusBank - Belarus, L. Makhist, Brest
Polytechnic - Belarus, and V. Piuri, Polytechnic of Milan - Italy
1:00PM - 2:00PM LUNCH
2:00PM - 3:40PM SESSION 12. SELF CHECKING CIRCUITS
Chair: B. Mitra, Texas Instruments - India
12.1 An Efficient Comparative Concurrent Built-In Self-Test Technique,
I. Voyiatzis, DEMOKRITOS - Greece, D. Nikolos, U. of Patras -
Greece, A. Paschalis, DEMOKRITOS - Greece, C. Halatsis, U. of Athens -
Greece, and Th. Haniotakis, DEMOKRITOS - Greece
12.2 Totally Self Checking Reconfigurable Duplication System with
Separate Internal Fault Location, N. Gaitanis, P. Kostarakis and
A. Paschalis, DEMOKRITOS - Greece
12.3*Generalized Modular Design of Testable m-out-of-n Code Checker,
G.P. Biswas and I. Sengupta, Indian Inst. of Tech. Kharagpur - India
12.4*A Graph Coloring Based Approach for Self-Checking Logic Circuit
Design, F.Y. Busaba and P.K. Lala, North Carolina A and T State U.
- USA
2:00PM - 3:40PM SESSION 13. DELAY TEST - II
Chair: Y. Min, ICT - China
13.1 Generation of Tenacious Tests for Small Gate Delay Faults in
Combinational Circuits, H. Takahashi, T. Watanabe and Y.
Takamatsu, Ehime U. - Japan
13.2 Functional Test Generation for Path Delay Faults, M.K. Srinivas,
Rutgers U. - USA, V.D. Agrawal, AT&T Bell Labs - USA, and
M.L. Bushnell, Rutgers U. - USA
13.3 Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault
Testing of Sequential Circuits, J.P. Hurst and N. Kanopoulos,
Research Triangle Inst. - USA
13.4 Sequential Logic Path Delay Test Generation by Symbolic Analysis,
S. Bose and V.D. Agrawal, AT&T Bell Labs - USA
3:40PM - 4:00PM TEA BREAK
4:00PM - 4:55PM SESSION 14. TECHNOLOGY-SPECIFIC TEST
Chair: M. Franklin, Clemson U. - USA
14.1 Low Power Design and Its Testability, H. Ueda and K. Kinoshita,
Osaka U. - Japan
14.2 Power Supply Current Detectability of SRAM Defects, J. Liu and
R. Makki, U. of North Carolina at Charlotte - USA
4:00PM - 4:55PM SESSION 15. DESIGN-SPECIFIC TEST
Chair: H. Fujiwara, NAIST - Japan
15.1 Fast Functional Testing of Delay-Insensitive Circuits, S. Pagey
15.2*DFT for Fast Testing of Self-Timed Control Circuits, S. Pagey
A. Khoche and E. Brunvand, U. of Utah - USA
15.3*Testing of a Parallel Ternary Multiplier Using I2L Logic, M. De
and B.P. Sinha, Indian Statistical Inst. - India
|