| IEEE Asian Test Symposium > |
3rd Asian Test Symposium, ATS'94
Third Asian Test Symposium(ATS'94)
November 15-17, 1994
Nara Ken New Public Hall, Nara, Japan
SPONSORED BY
IEEE Computer Society
Test Technology Technical Committee
IN COOPERATION WITH
Technical Group on Fault Tolerant Systems, IEICE
Techincal Group on VLSI Design Technology, IEICE
Special Interest Group on Design Automation, IPS Japan
Japan Society for the Promotion of Science, 132nd Committee
(Electron and Ion Beam Science and Technology)
Nara Institute of Science and Technology
SYMPOSIUM OVERVIEW
The Asian Test Symposium provides an international forum for engineers
and researchers from all countries of the world, especially from Asia,
to present and discuss various aspects of system, board, and device
testing with design, manufacturing, and field considerations in mind.
INVITATION TO NARA
Nara is often called the "cradle of Japanese civilization" or the
"fountainhead of Japan's art and culture." This city, 26 miles south of
Kyoto, is even older than Kyoto, having been the first permanent national
capital during the 8th century. We are pleased to propose hosting the
Third Asian Test Symposium, ATS'94, in this historic city, Nara, in 1994.
Following the symposia in Hiroshima and Beijing, this meeting in Nara also
aims at providing an Asian and international forum for the presentation
of the latest research and advanced development in test and design
technologies.
ORGANIZING COMMITTEE
Symposium Chair: Program Chair:
Hideo Fujiwara Yuzo Takamatsu
Nara Institute of Science Ehime University
and Technology takamatu(at)cs.ehime-u.ac.jp
fujiwara(at)is.naist.jp
Finance Chair: Publicity Chair:
Teruhiko Yamada Hideo Tamamoto
Meiji University Akita University
Publication Chair: Registration Chair:
Kiyoshi Furuya Kazumi Hatayama
Chuo University Hitachi Ltd.
furuya(at)ise.chuo-u.ac.jp hatayama(at)hrl.hitachi.co.jp
Local Arrangement Chair: Secretary:
Hiromi Hiraishi Akira Motohara
Kyoto Sangyo University Matsushita Co. Ltd.
hiraishi(at)kyoto-su.ac.jp motohara(at)vdrl.src.mei.co.jp
USA Liaison: European Liaison:
Jacob Savir Ad J.van de Goor
IBM Delf University of Technology
savir(at)vnet.ibm.com vdgoor(at)duteca.et.tudelft.nl
Ex Officio
Asian Group Chair, TTTC:
Kozo Kinoshita
Osaka University
kinoshita(at)ap.osaka-u.ac.jp
PROGRAM COMMITTEE MEMBERS
A.P.Ambler(U.K.) S.T.Chakradhar(USA) P.P.Chaudhuri(India)
T.Chen(China) B.Courtois(France)
A.J.van de Goor(Netherland) M.Hashizume(Japan) T.Hayashi(Japan)
F.Hirose(Japan) N.Ishiura(Japan) A.Ivanov(Canada)
K.Iwasaki(Japan) B.Kaminska(Canada) S.Kikuchi(Japan)
T.Kikuno(Japan) C.L.Lee(Taiwan) T.Manmoto(Japan)
Y.Min(China) T.Ogihara(Japan) J.Rajski(Canada)
A.Rubio(Spain) K.K.Saluja(USA) T.Sasao(Japan)
J.Savir(USA) S.C.Seth(USA) S.D.Sherlekar(India)
A.K.Somani(USA) M.Takada(Japan) N.Takagi(Japan)
M.Teramoto(Japan) P.Varma(USA) T.Yokohira(Japan)
C.W.Wu(Taiwan) H.J.Wunderlich(Germany) S.Xu(China)
A.Yamada(Japan) T.Yoneda(Japan) Y.Zorian(USA)
TECHNICAL PROGRAM
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Monday November 14th, 1994
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17:00 to 20:30 Registration(at Hotel Fujita Nara)
18:00 to 19:30 Welcome Reception(at Hotel Fujita Nara)
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Day 1: Tuesday November 15th, 1994
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9:00 to 9:30 Opening
9:30 to 10:00 Coffee break
10:00 to 11:40
Session 1A: Fault Simulation
Chair: A. Yamada (Tokyo Metropolitan University, Japan)
1A.1 "Test Generation and Fault Simulation Algorithms for
Sequential Circuits with Embedded RAMs," T.J. Chakraborty
and V.D. Agrawal (AT&T Bell Labs, USA).
1A.2 "Hardware-Accelerated Parallel-Pattern / Multiple-Fault-
Propagation Concurrent Fault Simulation," W. Hahn and
A. Hagerer (U. of Passau, Germany).
1A.3 "Fault Detection by Transient Transition Count Testing,"
K.C. Huang, M.Y.Chen, C.L.Lee (National Chiao Tung U., Taiwan),
and J.E Chen (Chung-Hua Polytech. Insti., Taiwan).
1A.4 "Delay Fault Propagation in Synchronous Sequential
Circuits," P. Cavallera, P. Girard, C. Landrault,
and S. Pravossoudovitch (U. Montpellier II, France).
Session 1B: On-line Testing
Chair: M. Nishihara (IBM Japan, Ltd., Japan)
1B.1 "Bounding Error Masking in Linear Output Space Compression
Schemes," S. Tarnick (The U. of Potsdam, Germany).
1B.2 "Fault Coverage Analysis in Monitored Sequential Circuits,"
R.A. Parekhji, G. Venkatesh, and S.D. Sherlekar
(Indian Insti. of Tech., India).
1B.3 "Application of Byte Error Detecting Codes to the Design
of Self-Checking Circuits," S. Pagey and A.J. Al-khalili
(Concordia U., Canada).
1B.4 "Strongly Fail Safe Interface Based on Concurrent Checking,"
M. Nicolaidis (TIMA/INPG, France).
11:40 to 13:30 Lunch
13:30 to 15:10
Session 2A: Test Pattern Generation and Parallel Testing
Chair: J. Rajski (McGill University, Canada)
2A.1 "Efficient Techniques for Multiple Fault Test Generation,"
S. Kajihara, R. Nishigaya, T. Sumioka, and K. Kinoshita
(Osaka U., Japan).
2A.2 "A Sequential Redundant Fault Identification Scheme and
Its Application to Test Generation," H.-C. Liang,
C.L. Lee (National Chiao Tung U., Taiwan), and
J.E Chen (Chung-Hua Polytech. Insti., Taiwan).
2A.3 "Test Scheduling Using Test Subsession Partitioning,"
D. Xiang (Academia Sinica, China).
2A.4 "On the Performance Analysis of Parallel Processing for
Test Generation," T. Inoue, T. Fujii, and H. Fujiwara
(Nara Insti. of Sci. and Tech., Japan).
Session 2B: Diagnostics
Chair: S. Xu (Shanghai University of Science and Technology, China)
2B.1 "An Efficient Logical Fault Diagnosis for Combinational
Circuits using Stuck-at Fault Simulation," T. Shimono
(NEC Co., Japan).
2B.2 "Efficiency Improvements for Multiple Fault Diagnosis of
Combinational Circuits," N. Yanagida, H. Takahashi, and
Y. Takamatsu (Ehime U., Japan).
2B.3 "An Approach of Diagnosing Single Bridging Faults in CMOS
Combinational Circuits," K. Yamazaki and T. Yamada
(Meiji U., Japan).
2B.4 "Efficient Diagnostic Fault Simulation for Sequential
Circuits," J.M. Jou and S.-C. Chen (National Cheng Kung U.,
Taiwan).
15:10 to 15:30 Coffee break
15:30 to 17:10
Session 3A: Test Pattern Generation
Chair: K. K. Salujya (University of Wisconsin, USA)
3A.1 "A Genetic Approach to Test Generation for Logic Circuits,"
T. Hayashi, H. Kita (Mie U., Japan), and K. Hatayama
(Hitachi Ltd., Japan).
3A.2 "Test Generation for Redundant Faults in Combinational
Circuits by Using Delay Effects," X. Yu, H. Takahashi,
and Y. Takamatsu (Ehime U., Japan).
3A.3 "Efficient Fault Ordering for Automatic Test Pattern
Generation for Sequential Circuits," P.A. Krauss and
M. Henftling (Tech. U. of Munich, Germany).
3A.4 "Sequential Test Generation in Massive Observability
Environments," P. Varma (CrossCheck Tech., USA).
Session 3B: Supply Current Testing
Chair: A. Rubio (Universitat Politecnica de Catalunya, Spain)
3B.1 "Testing of Analog Integrated Circuits Based on Power
Supply Current Monitoring and Discrimination Analysis,"
Z. Wang, G. Gielen, and W. Sansen (Katholieke U. Leuven,
Belgium).
3B.2 "Random Test Input Generation for Supply Current Testing
of TTL Combinational Circuits," M. Hashizume, I. Tsukimoto,
and T. Tamesada (The U. of Tokushima, Japan).
3B.3 "A Built-in IDDQ Test Circuit Utilizing Upper and Lower Limits,"
Y. Miura and S. Naito (Tokyo Metropolitan U., Japan).
3B.4 "The Effect of Fault Detection by IDDq Measurement for CMOS
VLSIs," J. Hirase and M. Hamada (Matsushita Ele. Co., Japan).
18:30 to 20:30 ATS'94 Banquet
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Day 2: Wednesday November 16 th, 1994
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9:00 to 10:15
Session 4A: Design for Testability I
Chair: B. Courtois (INPG/TIMA, France)
4A.1 "Testability Considerations in Technology Mapping,"
I. Pomeranz and S.M. Reddy (U. of Iowa, U.S.A.).
4A.2 "Easily Testable Realization for Generalized Reed-Muller
Expressions," T. Sasao (Kyushu Insti. of Tech., Japan).
4A.3 "C-Testable Multipliers Based on the Modified Booth
Algorithm," D. Gizopoulos (Insti. of Inf.&Telecom., Greece),
D. Nikolos (U. of Patras, Greece), and A. Paschalis
(Insti. of Inf.&Telecom., Greece) .
Session 4B: Fault Modeling
Chair: H. Khakzar (Fachhochschule fuer Technik Esslingen, Germany)
4B.1 "A Unified Model for Inter-Gate and Intra-Gate CMOS Bridging
Fault: The Configuration Ratio," M. Renovell, P. Huc, and
Y. Bertrand (U. de Montpellier II, France).
4B.2 "Detectability of Spurious Signals with Limited Propagation
in Combinational Circuits," F. Moll (U. Poli. de Catalunya,
Spain), M. Roca(U. Illes Balears, Spain), D. Marche
(Ecole Polytech. de Montreal, Canada), and A. Rubio
(U. Poli. de Catalunya, Spain).
4B.3 "On Crosstalk Fault Detection in Hierarchical VLSI Logic
Circuits," A. Liaud, J.Y. Fourniols, and E. Sicard
(INSA-DGE, France).
10:15 to 10:35 Coffee break
10:35 to 11:50
Session 5A: Design for Testability II
Chair: M. Takada (NEC Corporation, Japan)
5A.1 "Analysis and Improvement of Testability Measure Approximation
Algorithms," J. Bitner (The U. of Texas at Austin, USA),
J. Jain (Fujitsu Lab. of America), J. A. Abraham, and D. S. Fussell
(The U. of Texas at Austin, USA).
5A.2 "A New Testable Design of Logic Circuits under Highly Observable
Condition," W. Xiaoqing, H. Tamamoto (Akita U., Japan),
and K. Kinoshita (Osaka U., Japan).
5A.3 "Design in Fault Isolating of Ternary Cellular Arrays using
Ternary Decision Diagrams," N. Kamiura, H. Satoh, Y. Hata, and
K. Yamato (Himeji Insti. of Tech., Japan).
Session 5B: Software Testing
Chair: K. Matsumoto (Nara Institute of Science and Technology, Japan)
5B.1 "Software Design Verification using FTA," T. Fukaya,
M. Hirayama, and Y. Mihara (Toshiba Co., Japan).
5B.2 "Efficient Test Sequence Generation for Localization of Multiple
Faults in Communication Protocols," Y. Kakuda, H. Yukitomo,
S. Kusumoto, and T. Kikuno (Osaka U., Japan).
5B.3 "Netlist Automatic Extractor: An Image Processing Based Software for
Bare Board Test Data Generation," A. Benali, L. Balme(National
Polytech. Insti., France), and C. Vaucher (ZAC de la Fontaine de
Jouvence, France).
12:10 to 17:30 Tour to Horyuji and Yakushiji Temples
(including lunch time)
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Day 3: Thursday November 17th, 1994
====================================
9:00 to 10:15
Session 6A: Built-in Selt-Test I
Chair: S. D. Sherlekar (ASIC Technologies Pvt. Ltd., India)
6A.1 "Design of Random Pattern Testable Floating Point Adders,"
J. Rajski and J. Tyszer (McGill U., Canada).
6A.2 "Selecting Programmable Space Compactors for BIST Using Genetic
Algorithms," B. Tsuji (PMC-Sierra Inc., Canada), A. Ivanov
(U. of British Columbia, Canada), and Y. Zorian (AT&T Bell Labs,
USA).
6A.3 "Evaluations of Various TPG Circuits for Use in Two-Pattern
Testing," K. Furuya, S. Yamazaki, and M. Sato (Chuo U., Japan).
Session 6B: Verification I
Chair: J. Savir (IBM, USA)
6B.1 "Boolean Process - An Analytical Approach to Circuit
Representation," Y. Min (Academia Sinica, China).
6B.2 "Gate-Level Design Diagnosis Using a Learning-Based Search
Strategy, I. Pomeranz and S.M. Reddy (U. of Iowa, USA).
6B.3 "Design Verification by Using Universal Test Sets," B. Chen,
C. L. Lee (National Chiao Tung U., Taiwan), and J. E Chen
(Chung-Hua Polytech. Insti., Taiwan).
10:15 to 10:35 Coffee break
10:35 to 11:50
Session 7A: Built-in Self-Test II
Chair: C. W. Wu (National Tsing Hua University, Taiwan)
7A.1 "A Unified Method for Assembling Global Test Schedules,"
A. P. Stroele (U. of Karlsruhe, Germany) and H. J. Wunderlich
(U. of Siegen, Germany).
7A.2 "Design of Pseudo-Random Patterns with Low Linear Dependence and
Equi-Distribution," S. Matsufuji, S. Tadaki, and T. Yamanaka
(Saga U., Japan).
7A.3 "Minimum Test Sets for Locally Exhaustive Testing of Combinational
Circuits with Five Outputs," T. Yokohira, T. Shimizu, H. Michinishi,
Y. Sugiyama, and T. Okamoto (Okayama U., Japan).
Session 7B: Verification II
Chair: T. Yoneda (Tokyo Institute of Technology, Japan)
7B.1 "Time-Space Modal Model Checking towards Verification of Bit-Slice
Architecture," H. Hiraishi (Kyoto Sangyo U., Japan).
7B.2 "Automatic Test Generation for Functional Verification of
Microprocessors," J. Miyake, G. Brown, M. Ueda, and T. Nishiyama
(Matsushita Ele. Ind. Co., Japan).
7B.3 "Automatic Program Generation for Pipelined Processors,"
H. Iwashita, S.Kowatari, T. Nakata, and F. Hirose (Fujitsu Lab.
Ltd., Japan).
11:50 to 13:30 Lunch
13:30 to 14:45
Session 8A: Synthesis for Testability
Chair: A. Ivanov (University of British Columbia, Canada)
8A.1 "Testable Synthesis and Testing of Finite State Machines,"
C. -Y. Liu and K. K. Saluja (U. of Wisconsin, USA).
8A.2 "On Full Path Delay Fault Testability of Combinational Circuits,"
X. Xie and A. Albicki (U. of Rochester, USA).
8A.3 "Data Path Synthesis for Easy Testability," M.K.Dhodhi, I. Ahmad,
and A. A. Ismaeel (Kuwait U., Kuwait).
Session 8B: Test Cost Reduction
Chair: A. Motohara (Matsushita Electric Industrial Co. Ltd., Japan)
8B.1 "Two Technologies for Minimizing Power Dissipation in Scan Circuits
During Test Application,"
S. Chakravarty and V. Dabholkar (State U. of New York at Buffalo, USA).
8B.2 "Test Time Reduction for Scan-Designed Circuits by Sliding
Compatibility," J.-S. Chang and C.-S. Lin (National Taiwan U., Taiwan).
8B.3 "A Partial Scan Algorithm Based on Reduced Scan Shift," Y. Higami,
S. Kajihara, and K. Kinoshita (Osaka U., Japan).
14:45 to 15:05 Coffee break
15:05 to 16:45
Session 9A: Diagnostics and Fault-Tolerant Systems
Chair: Y. Zorian (AT&T Bell Lab., USA)
9A.1 "Experiment of Faults on the "Happa" System and a Proposal of
Backup RAM Technique," K. Iwasaki, H. Yoshikawa, and A. Furuta
(Chiba U., Japan).
9A.2 "A Diagnostic Network for Massively Parallel Processing Systems,"
Y.-H. Choi and Y.-S. Kim (Honglk U., Korea).
9A.3 "Design and Evaluation of Fault-Tolerant Interleaved Memory
Systems," S.-K. Lu, S.-Y. Kuo (National Taiwan U., Taiwan), and
C-W. Wu (National Tsin Hua U., Taiwan).
9A.4 "Switching Networks and Neural Algorithms for Reconstructing
Mesh-Connected Processor Arrays with Spares on Their Sides,"
I. Takanami (Iwate U., Japan), Y. Hisanaga, and K. Inoue
(Yamaguchi U., Japan).
Session 9B: Analog and Adaptive Testing
Chair: S. Kikuchi (Hitachi Ltd., Japan)
9B.1 "A Fault Diagnosis Technique for Subranging ADCs," A. Charoenrook
and M. Soma (U. of Washington, USA).
9B.2 "A New Built-In Self-Test Approach for Medium to High-Resolution
Digital-to-Analog Converters," K. Arabi, B. Kaminska (Ecole Polytech.
de Montreal, Canada), and J. Rzeszut (Warsaw U. of Tech., Poland).
9B.3 "Characteristics of a Fuzzy Test System," T. Koyama (Tokushima
Bunri Univ., Japan).
9B.4 "To Verify Manufacturing Yield by Testing," M.-J. Wang, J.-E Chen,
and Y.-Y. Chen (Chung-Hua Polytech. Insti., Taiwan).
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REGISTRATION:
Registration fees: Before Oct.14, 1994 After Oct. 14, 1994
IEEE Member 41,000 yen 49,000 yen
Non-member 52,000 yen 62,000 yen
Student 7,000 yen 9,000 yen
This fee includes reception, banquet, coffee breaks, a copy of symposium
proceedings. The student fee does not include reception and banquet.
HOTEL RESERVATION:
For hotel reservation, please contact JTB kyoto Office. ATS discount
will be available.
JTB Kyoto Office
Higashi-Shiokoji-cho, Shimogyo-ku, Kyoto 600, JAPAN
Phone: +81-75-361-7241 Telefax: +81-75-341-1028
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* For more information please contact Hideo Tamamoto *
* (tamamoto(at)ie.akita-u.ac.jp), Publicity Chair, by e-mail. *
* You can get a printed version of advance program which *
* includes a registration form and a hotel application form. *
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