First Asian Test Symposium(ATS'92)

        November 26-27, 1992
        Hiroshima Grand Hotel, Hiroshima, Japan

Sponsored by
        IEEE COMPUTER SOCIETY
        TEST TECHNOLOGY TECHNICAL COMMITTEE
In Cooperation with
        SPECIAL INTEREST GROUP ON DESIGN AUTOMATION
        INFORMATION PROCESSING SOCIETY OF JAPAN
        TECHNICAL GROUP ON FAULT TOLERANT SYSTEMS
        IEICE
        JAPAN SOCIETY FOR THE PROMOTION OF SCIENCE, 132ND COMMITTEE
        (ELECTRON AND ION BEAM SCIENCE AND TECHNOLOGY)

COMMITTEES:

        Symposium Chair
        Kozo Kinoshita
        Osaka University

        Program Chair
        Hideo Fujiwara
        Meiji University

        Finance Chair
        Hiromi Hiraishi
        Kyoto Sangyo University

        Publicity Chair
        Akihiko Yamada
        NEC Corporation

        Publication Chair
        Kiyoshi Furuya
        Chuo University

        Registration Chair
        Fumiyasu Hirose
        Fujitsu Lab. Ltd.

        Local Arrangement Chair
        Yuzo Takamatsu
        Ehime University

        Secretary
        Teruhiko Yamada
        Meiji University

        USA Liaison
        Jacob Savir
        IBM

PROGRAM COMMITTEE MEMBERS:
        T. Chen
        M. Fujita
        K. Hatayama
        Y. Igushi
        N. Ishiura
        K. Iwasaki
        M. Kawamura
        Y. Min
        A. Motohara
        T. Ogihara
        K. Okumura
        S. M. Reddy
        P. Sardeshmukh
        T. Sasao
        J. Savir
        S. D. Sherlekar
        T. Shimono
        N. Takagi
        H. Tamamoto
        M. Teramoto
        E. Trischler
        T. Yoneda

PROGRAM: 

SESSION 1:  Verification and Compaction
- Formal Verification of Fail-Safeness of a Comparator for Redundant System
Using Regular Temporal Logic, K.Kawakubo and H.Hiraishi (Fukuyama Univ. and
Kyoto Sangyo Univ., Japan)
- Behavioral Design and Test Assistance for Pipelined Processors,
H.Iwashita, T.Nakata, and F.Hirose (Fujitsu Labs. Ltd. , Japan)
- Minimum Verification Test Set for Combinational Circuit, H.Michinishi,
T.Yokohira and T.Okamoto (Okayama Univ., Japan)
- Test Set Compaction for Combinational Circuits, J.-S. Chang and C.-S. Lin
(National Taiwan Univ., Taiwan)

SESSION 2:  Fault Simulation
- Fault Simulation Based on Value Difference, C. P. Wu, C. L. Lee and W. Z.
Shen (National Chiao Tung Univ., Taiwan)
- Accelerated Fault Simulation Utilizing Multiple-Fault Propagation,
Y.Xing, G.van Brakel, and H.G.Kerkhoff (Univ. of Twente, the Netherlands)
- Reduction of Dynamic Memory Usage in Concurrent Fault Simulation for
Synchronous Sequential Circuits, K.Kim and K.K.Saluja (Univ. of Wisconsin,
USA)
- Highly Efficient Fault Simulation Exploiting Hierarchy in Circuit
Description, B.H.Seiss and H.C.Wittmann (Technical Univ. of Munich,
Germany)
- Path Delay Fault Simulation Algorithms for Sequential Circuits,
T.J.Chakraborty, V.D.Agrawal and M.L.Bushnell (AT&T Bell Labs. and Rutgers
Univ., USA)

SESSION 3:  Test Pattern Generation
- Test Input Vectors for Supply Current Testing of TTL Combinational
Circuits, M.Hashizume, T.Tamesada and I.Tsukimoto (Tokushima University,
Japan)
- Quiescent Current Testing of Combinational Circuits with Bridging Faults,
M. Roca and A. Rubio (Universitat Politecnica de Catalunya, Spain )
- A Current Testing for CMOS Logic Circuits Applying Random Patterns and
Monitoring Dynamic Power Supply Current, H.Tamamoto, H.Yokoyama and
Y.Narita (Akita Univ., Japan)
- A Complement-Based Fast Algorithm to Generate Universal Test Sets for
Combinational Function Blocks, B.Chen and C.L.Lee (National Chiao Tung
Univ., Taiwan)
- Localization and Aftereffect of Automatic Test Generation,  Z.Li, Y.Pan,
and Y.Min (Academia Sinica , China)
- Practical Considerations in ATPG Using CrossCheck Technology,  S.Chandra,
N.Jacobson and G.Srinath (CrossCheck Tech., Inc. , USA)

SESSION 4:  Functional Testing
- Functional Tests for Arbitration SRAM-type FIFOs, Ad J. van de Goor and
Y. Zorian (Delft Univ. of Technology, The Netherlands  and AT&T Bell Labs.,
USA)
- Functional Testing by Process Flowcharts of Microprocessor Based Circuits
for Sequence Control, E.Tasaka, M.Hashizume, T.Yamazoe, T.Tamesada and
T.Kayahara (Tokushima Univ., Japan )
- Issues in Fault Modelling and Testing of Micropipelines Sandeep Pagey,
S.D.Sherlekar and G.Venkatesh (Indian Institute of Technology, India)
- Automatic Behavioral Test Pattern Generation for Digital Circuits, N.
Giambiasi, J.F.Santucci, and A.L.Courbis (LERI. , France)
- Methods to Measure and to Enhance the Testability of Behavioral
Descriptions of Digital Circuits, N. Giambiasi, J.F.Santucci, M.Boumedine
and G.Dray (LERI., France)
- Cyclogen: Hierarchical, Functional-Level Test Generator Based on
Cyclomatic Complexity Measure and on ROBDD Representation, B.Ayari and
B.Kaminska (Ecole Polytechnique de Montreal, Canada)

SESSION 5:  On-Line Testing
- Techniques for Reducing Hardware Requirement of Self Checking
Combinational Circuits, S. Pagey, S.D.Sherlekar and G.Venkatesh (Indian
Institute of Tech., India)
- A Concurrent Fault Detection Method for Superscalar Processors, A. P.
Pawlovsky and M. Hanawa (Hitachi  Ltd., Japan) 
- A Control Constrained Test Scheduling Approach for VLSI Circuits,
S.Misra, S.Subramanian, and P.P.Chaudhuri (Motorola India Electronics Pvt.
Ltd., India)
- On Reducing Test Time and Meeting Deadline in Real-Time Systems,
T.R.Sarnaik and A.K.Somani (Univ. of Washington, USA)

SESSION 6:  Diagnostics
- Laser Injection of Spot Defects on Integrated Circuits, R.Velazco,
B.Martinet, and G.Auvert (Institut IMAG, France)
- Novel Image-based LSI Diagnostic Method Using E-beam without CAD
Database, T.Nakamura, Y.Hanagama, K.Nikawa, T.Tsujide, K.Morohashi and
K.Kanai (NEC Corp., Japan)
- A Method of Diagnosing Logical Faults in Combinational Circuits,
K.Yamazaki and T.Yamada (Meiji Univ., Japan)
- Break Fault Model and Fault Collapsing Analysis for PLA's, G.Hwang and
W.Z. Shen (National Chiao Tung Univ., Taiwan)
- A Practical Approach for the Diagnosis of  a MIMD Network, C.Aktouf,
G.Mazare, C.Robach, and R.Velazco (IMAG/LGI, France)
- Three-Valued Computer System Diagnosis Implemented by Artificial Neural
Network, T.Chen, K.Wu, and R.Yao (Chongqing Univ., China)

SESSION 7:  Testability Techniques
- Synthesis for Testability of PLA Based Finite State Machines,
M.J.Avedillo, J.M.Quintana and J.L.Huertas (Centro Nacional de
Microelectronica, Spain)
- Synthesis of Easily Testable Sequential Circuits with Checking Sequences,
S.Shibatani and K.Kinoshita (Osaka Univ., Japan)
- A Test Application Scheme for Embedded Full-Scan Circuits to Reduce
Testing Costs, S.M. Reddy and I.Pomeranz (Univ. of Iowa, USA)
- An Approach to Design-for-Testability for Memory Embedded Logic LSIs,
K.Hatayama, T.Hayashi, M.Takakura, T.Suzuki, S.Michishita, and H.Satoh
(Hitachi Ltd., Japan)
- Syndrome Testable Design Software Package and Instruments and Syndrome
Testing System for Sequential Circuits, W. F. Lai and W. J. Jie (Shanghai
Univ. of Science and Tech., China)
- Design for Testability in a 200 MFLOPS Vector-Pipelined Processor
(VPP)-ULSI, Y.Hagihara, C.Ohkubo, F.Okamoto, H.Yamada, M.Takada and
T.Enomoto (NEC Corp., Japan)

SESSION 8:  Built-In Self-Test
- Exhaustive Two-Pattern Generation with Cellular Automata, S.Nandi, S.Roy,
M.Sharma, and P.Pal Chaudhuri (Indian Institute of Tech., India)
- Synthesis of Autonomous TPG Circuits Oriented for Two-Pattern Testing,
K.Furuya, S.Seki and E.J.McCluskey (Chuo Univ., Japan and Stanford Univ.,
USA)
- Accumulator-Based Compaction for Built-In Self Test of Data-Path
Architectures, J. Rajski, J. Tyszer and M. Kassab (McGill Univ., Canada)
- A Fuzzy Multiple Signature Compaction Scheme for BIST, Y. Wu and A.
Ivanov (Univ.of British Columbia, Canada)
- Reducing BIST Hardware by Test Schedule Optimization, A. P. Stroele
(Univ. of Karlsruhe, Germany)