2007 IEEE 16th Asian Test Symposium (ATS’07)

Advance Program

October 9-11, 2007, Beijing Friendship Hotel, Beijing, China

Session 1A-Opening Session

Session 2A- Fault Modeling and Functional Test

• 146) The Region-Exhaustive Fault Model
  Abhijit JAS (Intel Corporation - USA), SURIYAPRAKASH NATARAJAN (Intel Corporation - USA), Srinivas PATIL (Intel Corporation - USA)
• 3) Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation
  Irith POMERANZ (Purdue University - USA), Praveen PARVATHALA (Intel - USA), Srinivas PATIL (Intel Corporation - USA)
• 148) Mining Sequential Constraints for Pseudo-Functional Testing
  WEIXIN WU (Virginia Tech. - USA), Michael HSIAO (Virginia Tech - USA)

Session 2B- SOC Test

• 33) Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip
  Thomas Edison YU (Nara Institute of Science and Technology - Japan), Tomokazu YONEDA (Nara Institute of Science and Technology - Japan), Krishnendu CHAKRABARTY (Duke University - USA), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
• 97) Design Reuse of on/off-Chip Bus Bridge for Efficient Test Access to AMBA-based SoC
  JAEHOON SONG (Hanyang University - Korea), JUHEE HAN (Hanyang University - Korea), Dooyoung KIM (Hanyang University - ), Hyunbean YI (Hanyang University - Korea), Sungju PARK (Hanyang University - Korea)
• 22) Test Scheduling for Memory Cores with Built-In Self-Repair
  Tomokazu YONEDA (Nara Institute of Science and Technology - Japan), Yuusuke FUKUDA (Nara Institute of Science and Technology - ), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)

Session 2C- Power Aware Test I

• 122) Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits
  Michel RENOVELL (LIRMM - France), Laurent LARGUIER (LIRMM - France), Florence AZAIS (LIRMM - CNRS / Univ Montpellier 2 - France)
• 14) Effect of IR-Drop on Path Delay Testing Using Statistical Analysis
  Chunsheng LIU (Univ. of Nebraska - USA), Yu HUANG (Mentor Graphics Co. - USA), Yang WU (Univ. of Nebraska - USA)
• 166) Low Power Reduced Pin Count Test Methodology
  Krishna CHAKRAVADHANULA (Cadence Design Systems - USA), Nitin PARIMI (Cadence Design Systems - ), BRIAN FOUTZ (Cadence Design Systems - USA), Bing LI (Cadence Design Systems - ), Vivek CHICKERMANE (Cadence Design Systems - )

Session 3A- Test Compression

• 25) A High Compression and Short Test Sequence Test Compression Technique to Enhance Compressions of LFSR Reseeding
  Seongmoon WANG (NEC Labs America - USA), Wenlong WEI (NEC Labs., America - ), srimat CHAKRADHAR (NEC Labs., America - )
• 151s) A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decomposition
  Aiman EL-MALEH (King Fahd University of Petroleum&Minerals - Saudi Arabia), MUSTAFA ALI (King Fahd Unversity of Petroleum&Minerals - Saudi Arabia), Ahmad AL-YAMANI (King Fahd University of Petroleum and Minerals - )
• 127s) Test Compression / Decompression Based on JPEG VLC Algorithm
  Hideyuki ICHIHARA (Hiroshima City University - Japan), Yukinori SETOHARA (Hiroshima City University - ), Yusuke NAKASHIMA (Hiroshima City University - ), Tomoo INOUE (Hiroshima City Univ. - Japan)
• 121s) Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture
  Sying-Jyan WANG (National Chung-Hsing University - Taiwan), Po-Chang TSAI (National Chung-Hsing University - ), Hung-Ming WENG (National Chung-Hsing University - ), KATHERINE SHU-MIN LI (Electronics Engineering Department, National Chung-Tung University - Taiwan)

Session 3B- Fault Diagnosis I

• 82) Fast Bridging Fault Diagnosis using Logic Information
  ALBERTO BOSIO (LIRMM - France), Patrick GIRARD (LIRMM - France), Serge PRAVOSSOUDOVITCH (LIRMM - France), Christian LANDRAULT (LIRMM - France), Arnaud VIRAZEL (LIRMM - France), Alexandre ROUSSET (LIRMM - France)
• 144) Fault Dictionary Based Scan Chain Failure Diagnosis
  Ruifeng GUO (Mentor Graphics Corp. - USA), Yu HUANG (Mentor Graphics Co. - USA), Wu-Tung CHENG (Mentor Graphics Corporation - USA)
• 164) An Efficient Diagnostic Test Pattern Generation Framework Using Boolean Satisfiability
  Feijun ZHENG (Zhejiang University - China), Kwang-Ting Cheng (University of California at Santa Barbara, CA, USA), Xiaolang Yan(Zhejiang University - China)

Session 3C-panel 1

Session 4A- Delay Test I

• 31s) False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults
  YUKI YOSHIKAWA (NAIST - Japan), Satoshi OHTAKE (Nara Institute of Science and Technology - Japan), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
• 155s) Using Programmable On-Product Clock Generation (OPCG) for Delay Test
  Brion KELLER (Cadence Design Systems - USA), MD ANIS UZZAMAN (Cadence Design Systems, Inc. - USA), Bibo LI (Cadence Design Systems, Inc. - USA), Tom SNETHEN (Cadence Design Systems, Inc. - )
• 96s) An On-Line BIST Technique for Delay Fault Detection in CMOS Circuits
  ELHAM KHAYAT MOGHADDAM (Sharif University of Technology - Iran), shaahin HESSABI (sharif University of Technology - )

Session 4B- DFT I

• 125s) Optimum Test Set for Bridging Faults Detection in Reversible Circuits
  HAFIZUR RAHAMAN (Bengal Engg. and Science University, shibpur - India), Dipak KOLE (PhD student - India), DEBESH K DAS ( - ), BHARGAB B BHATTACHARYA (Indian Statistical Inst - India)
• 132s) Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis
  Sying-Jyan WANG (National Chung-Hsing University - Taiwan), Xin-Long LI (National Chung-Hsing University - ), KATHERINE SHU-MIN LI (Electronics Engineering Department, National Chung-Tung University - Taiwan)
• 89s) A RTL Testability Analyzer Based on Logical Virtual Prototyping
  Yu HUANG (Mentor Graphics Co. - USA), Nilanjan MUKHERJEE (Mentor Graphics - USA), Wu-Tung CHENG (Mentor Graphics Corporation - USA)

Session 4C- Software Test

• 133) A Novel Test Case Generation Method of Pair-Wise Testing
  FENG-AN QIAN, Jian-hui Jiang (Tongji University - China)
• 80s) A New Concept of Software Reliability Measurements
  Shiyi XU (Shanghai University - China)
• 56s) Regression Testing Based-on Slicing of Component-based Software Architectures
  JAIPRAKASH LALLCHANDANI (Indian Institute of Technology Kharagpur - India), Rajib MALL (IIT Kharagpur - )

Session 5A- Test Generation I

• 91) Improving timing-independent testing of crosstalk using realistic assumptions on delay faults
  Shahdad IRAJPOUR (University of Southern California - USA), Sandeep GUPTA (University of Southern California - USA), Melvin BREUER (USC - )
• 53) Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects
  MINJIN ZHANG (Institute of Computing Technology,Chinese Academy of Sciences - China), Xiaowei LI (Chinese Academy of Sciences - China)
• 76) Simulating Open-Via Defects
  Stefan SPINNER (Uni Freiburg - ), Jie JIANG (Uni Freiburg - ), Ilia POLIAN (Albert-Ludwigs-University of Freiburg - Germany), Piet ENGELKE (Albert Ludwigs University - Germany), Bernd BECKER (University of Freiburg - Germany)

Session 5B- Design Verification

• 95) An Accurate Analysis of Microprocessor Design Verification
  HAIHUA SHEN (Institute of Computing Technology - China), Heng ZHANG (Institute of Computing Technology - ), weiwu HU (ict cas - )
• 61) Optimized Assignment Coverage Estimation in Formal Verification of Digital Systems
  MAJID NABI (Tehran University - Iran), Hamid SHOJAEI (Iran - ), Zainalabedin NAVABI (Northeastern University - USA)
• 123) EHSAT Modeling from Algorithm Description for RTL Model Checking
  XIAOQING YANG (Tsinghua University - China), Jinian BIAN (Tsinghua University, China - China), SHUJUN DENG (Tsinghua University - China), Yanni ZHAO (Tsinghua University - )

Session 5C-Panel 2

Session 6A- Test Generation II

• 77) SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges
  Piet ENGELKE (Albert Ludwigs University - Germany), Bettina BRAITLING (Uni Freiburg - ), Ilia POLIAN (Albert-Ludwigs-University of Freiburg - Germany), Michel RENOVELL (LIRMM - France), Bernd BECKER (University of Freiburg - Germany)
• 70) Improving Test Pattern Compactness in SAT-based ATPG
  STEPHAN EGGERSGLÜß ( - ), ROLF DRECHSLER (University of Bremen - Germany)
• 158) Symbolic Path Sensitization Analysis and Applications
  Jian KANG (University of Nebraska - Lincoln - USA), Sharad SETH (Univ of Nebraska - USA), Shashank MEHTA (indian institute of technology - )

Session 6B- Fault Diagnosis II

• 94) Improving Performance of Effect-Cause Diagnosis with Minimal Memory Overhead
  Huaxing TANG (Mentor Graphics Corporation - USA), Chen LIU (University of Iowa - ), Wu-Tung CHENG (Mentor Graphics Corporation - USA), Sudhakar REDDY (University of Iowa - USA), Wei ZOU (Mentor Graphics - USA)
• 50) Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines
  Hiroshi TAKAHASHI (Ehime University - Japan), Yoshinobu HIGAMI (Ehime University - Japan), Hiroyuki YOTSUYANAGI (University of Tokushima - Japan), Yuzo TAKAMATSU (Ehime Univ. - ), Takashi AIKYO (Semiconductor Technology Academic Research Centor - Japan), Koji YAMAZAKI (Meiji University - Japan)
• 90) Programmable Logic BIST for At-speed Test and Silicon Debug
  Yu HUANG (Mentor Graphics Co. - USA), Xijiang LIN (Mentor Graphics Corp. - USA)

Session 6C- Power Aware Test II

• 110) Resistive Bridging Faults DFT with Adaptive Power Management Awareness
  Urban INGELSSON (University of Southampton - United Kingdom), PAUL M ROSINGER (University of Southampton - United Kingdom), S. Saqib KHURSHEED (King Fahd University of Petroleum and Minerals - Saudi Arabia), Bashir AL-HASHIMI (University of Southampton - United Kingdom), Peter HARROD (ARM LTD - United Kingdom)
• 160s) An Efficient Peak Power Reduction Technique for Scan Testing
  Kai-Shun HU (National Taiwan University - ), Meng-Fan WU (National Taiwan University - ), Jiun Lang HUANG (National Taiwan University - Taiwan)
• 105s) Power-Conscious Multi-Frequency Modular Testing of SoCs with Dynamic Reconfiguration of Multi-Port ATE
  Dan ZHAO (University of Louisiana at Lafayette - USA), Ronghua HUANG (UL Lafayette - USA), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
• 27s) High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects
  SUNGHOON CHUN (Yonsei University - Korea), Yongjoon KIM (Yonsei University - Korea), Sungho KANG (Yonsei University - Korea)

Session 7A- Soft Error Issue

• 118) Improving circuit robustness with cost-effective soft-error-tolerant sequential elements
  MINGJING CHEN (University of California, San Diego - USA), Alex ORAILOGLU (University of California at San Diego - USA)
• 8) CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors
  SHIJIAN ZHANG (ict cas - China), weiwu HU (ict cas - )
• 167s) Monitoring Transient Errors in Sequential Circuits
  RAMASHIS DAS (University of Michigan - USA), JOHN HAYES (University of Michigan - USA)
• 139s) a frequency analysis model for propagation of transient errors in combinational logic
  SHAOHUA LEI, Yinhe Han, and Xiaowei Li(institute of computing technology, chinese academy of sciences - China)

Session 7B- DFT II

• 13) Scan Testing for Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost
  Dong XIANG (Tsinghua University - China), Krishnendu CHAKRABARTY (Duke University - USA), Dianwei HU (Tsinghua University - ), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
• 163) Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan
  GEFU XU (auburn university - USA), Adit SINGH (Auburn University - USA)
• 101) An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing
  XIAOXIN FAN (Institute of Computing Technology, Chinese Academy of Sciences - China), Yu HU (Institute of Computing Technology, Chinese Academy of Sciences - China), Laung-Terng WANG (Syntest, Inc. - )

Session 7C-Industry

• Industry–01) High-Speed Coaxial Contact Assembly (CCA) for Wafer Test Probe Card
  Sang-Hoon Lee, Gyu-Yeol Kim, Young-Soo An, Se-Jang Oh and Ki-Sang Kang (Samsung Electronics, Korea)
• Industry–03) I DDQ Test Challenges in Nanotechnologies:A Manufacturing Test Strategy
  Yu Wei P’ng, Moo Kit Lee, Peng Weng Ng, Chin Hu Ong (Marvell Semiconductor, Malaysia)
• Industry–05) Experimental Results of Transition Fault Simulation with DC Scan Tests
  Wataru Kawamura (Sony Corporation, Japan)
• Industry–06) A Review of Power Strategies for DFT and ATPG
  Brion Keller and Tom Jackson (Cadence Design Systems, Inc., USA)
• Industry–07) Concurrent Test Implementations
  Shawn Molavi, Toby McPheeters (Broadcom Corporation, USA)
• Industry – 09) Scan Diagnosis and Its Successful Industrial Applications-- Yield Improvement, Verified Flow, Accuracy, Layout Aware and Volume Diagnosis
  Wu Yang,  Wu-tung Cheng, Martin Keim, Yu Huang and Randy Klingenberg (Mentor Graphics, USA)

Session 8A- Current Test

• 169) Testing RF Components with Current Signatures
  Selim AKBAY (Georgia Institute of Technology - USA), Shreyas SEN (Georgia Institute of Technology - ), Abhijit CHATTERJEE (Georgia Institute of Technology - USA)
• 156) Implementation of Defect Oriented Testing and ICCQ testing for industrial mixed-signal IC
  Liquan FANG (NXP Semiconductors - Netherlands), Yang ZHONG (RWTH-Aachen University - ), Henk VAN DE DONK (NXP Semiconductors - ), yizi XING (NXP Semiconductors - )
• 106) Current Testable Design of Resistor String DACs
  Masaki HASHIZUME (Tokushima Univ - Japan), Yutaka HATA (The University of Tokushima - ), Tomomi NISHIDA (The University of Tokushima - ), Hiroyuki YOTSUYANAGI (University of Tokushima - Japan), Yukiya MIURA (Tokyo Metropolitan Univ. - Japan)

Session 8B- NOC/SOC Test

• 170) An HDL-Based Platform for High Level NoC Switch Testing
  Zainalabedin NAVABI (Northeastern University - USA), Mahshid SEDGHY (University of Tehran - ), Armin ALAGHI (University of Tehran - ), Elnaz KOOPAHI (University of Tehran - Iran)
• 16s) Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing
  Fawnizu Azmadi HUSSIN (Nara Institute of Science and Technology - Japan), Tomokazu YONEDA (Nara Institute of Science and Technology - Japan), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)
• 135s) A Scheme of Test Data Compression with Block Marking and Updating Coding for SoC
  Zhang LEI, Huaguo Liang, Wenfa Zhan and Cuiyun Jiang (School of Computer and Information, Hefei University of Technology, Hefei, China)
• 150s) Test Efficiency Analysis and Improvement for SOC Test Platforms
  Tong-Yu HSIEH (National Cheng Kung University - Taiwan), Kuen Jong LEE (National Cheng-Kung Univ - Taiwan), Jian-Jhih YOU (National Cheng Kung University - )

Session 8C-Panel 3

Session 8D-Special Session on Analog Production Test #1

• APT1.1) Issues Regarding New Product Release to Semiconductor Manufacturing
  Choon-Sang Chew (National Semiconductor)
• APT1.2) How The Noise Floor Affects The Production Yield
  Akinori Maeda (Verigy, Japan), K.K. Hachioji (Tokyo, Japan)
• APT1.3) Integrated Test Solution for embedded UHF/RF SOC
  Sean Lu (Broadcom Corporation, Irvine, CA), Dee-Won Lee (Verigy Ltd., Irvine, CA)
• APT1.4) Production Test of High Volume Commercial RFIC
  Friedrich Taenzler (Texas Instruments, Dallas)

Session 9A- BIST

• 30) Programmable Scan-Based Logic Built-In Self Test
  Liyang LAI (Mentor Graphics Corporation - USA), Wu-Tung CHENG (Mentor Graphics Corporation - USA), Thomas RINDERKNECHT (Mentor Graphics - )
• 84) Evaluation of a BIST technique for CMOS imager
  LIVIER LIZARRAGA (TIMA - France), Salvador MIR (TIMA Laboratory - France), Gilles SICARD (Tima - )
• 93) Built-In Speed Grading with a Process-Tolerant ADPLL
  Hsuan-Jung HSU (National Tsing-Hua University, Taiwan - ), Chun-Chien TU (NTHU - ), Shi-Yu HUANG (National Tsing-Hua University - Taiwan)

Session 9B- Memory Test I

• 138) A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories
  LI-MING DENQ (National Tsing Hua University - Taiwan), Cheng-Wen WU (National Tsing Hua University - Taiwan)
• 162) Testing Comparison Faults of Ternary Content Addressable Memories with Asymmetric Cells
  JIN-FU LI (National Central University - Taiwan)
• 115) CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs
  HSIANG-HUANG WU (Realtek Semiconductor Corp. - Taiwan), Jin-Fu Li, Chi-Feng Wu, and Cheng-Wen Wu

Session 9C- Power Aware Test III

• 39) Scan Power Reduction through Scan Architecture Modification and Test Vector Reordering
  CHANDAN GIRI (Inidian Institute of Technology Kharagpur - India), Pradeep Kumar CHOUDHARY (IIT Kharagpur, India - ), Santanu CHATTOPADHYAY (Indian Institute of Technology Kharagpur, India - )
• 130) Low-Capture-Power Test Generation by Specifying Minimum Set of Controlling Inputs
  Nan-Cheng LAI (National Chung-Hsing University - ), Sying-Jyan WANG (National Chung-Hsing University - Taiwan)
• 67) Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique
  Bo-Hua CHEN (National Taiwan University - ), Wei-Chung KAO (National Taiwan University - Taiwan), BING-CHUAN BAI (National Taiwan University - Taiwan), Shyue-Tsong SHEN (National Taiwan University - ), James LI (National Taiwan University - Taiwan)

Session 9D-Special Session on Analog Production Test #2

• APT2.1) Bluetooth Hopping BER Testing Methodologies on a Production Test Platform
  David Bement, David Karr ( Broadcom Corporation)
• APT2.2) Understanding GSM/EDGE Modulated Signal Test on Cellular BB SOC
  Deng Yue (Verigy Shanghai Application Development Center)
• APT2.3) Top 5 Issues in Practical Testing of High-Speed Interface Devices
  Takahiro J. Yamaguchi, Advantest Laboratories (Ltd., Sendai, Miyagi, Japan)

Session 10A- Delay Test II

• 2) Enhanced Broadside Testing for Improved Transition Fault Coverage
  Irith POMERANZ (Purdue University - USA), Sudhakar REDDY (University of Iowa - USA)
• 152) On generating vectors that invoke high circuit delays – Delay testing and dynamic timing analysis
  Ide HUANG (USC - USA), Sandeep GUPTA (University of Southern California - USA)
• 28) Test Generation for Timing Critical Transition Faults
  Xijiang LIN (Mentor Graphics Corp. - USA)

Session 10B- Analog Test

• 73) A 2-ps Resolution Wide Range BIST Circuit for Jitter Measurement
  NAI-CHEN DANIEL CHENG (Industrial Technology Research Center - Taiwan), Yu Lee, and Ji-Jan Chen
• 161) An Accurate Jitter Estimation Technique for Efficient High Speed I/O Testing
  Dongwoo HONG (University of California, Santa Barbara - USA), KWANG-TING CHENG (UC Santa Barbara - USA)
• 11) Test Point Selections for a Programmable Gain Amplifier Using NIST and Wavelet Transform Methods
  Xinsong ZHANG (University of Arkansas - USA), SIMON ANG (University of Arkansas - USA), Chandra CARTER (Texas Instruments - USA)

Session 10C-Panel 4

Session 11A- Test Generation III

• 40s) Test Generation for Transistor Shorts using Stuck-at Fault Simulator and Test Generator
  Yoshinobu HIGAMI (Ehime University - Japan), Kewal SALUJA (Univ. of Wisconsin - Madison - USA), Hiroshi TAKAHASHI (Ehime University - Japan), Shin-ya KOBAYASHI (Ehime Univ. - ), Yuzo TAKAMATSU (Ehime Univ. - )
• 1s) Diagnostic Test Generation Targeting Equivalence Classes
  Irith POMERANZ (Purdue University - USA), Sudhakar REDDY (University of Iowa - USA)
• 108s) Fault-dependent/independent Test generation Methods for State Observable FSMs
  Toshinori HOSOKAWA (Nihon University - Japan), Ryoichi INOUE (Nihon University - ), Hideo FUJIWARA (Nara Institute of Science and Technology - Japan)

Session 11B- Memory Test II

• 42s) Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior
  Magali BASTIAN (Infineon Technologies - France), Vincent GUOIN (Infineon - ), Patrick GIRARD (LIRMM - France), Christian LANDRAULT (LIRMM - France), Alexandre NEY (LIRMM - ), Serge PRAVOSSOUDOVITCH (LIRMM - France), Arnaud VIRAZEL (LIRMM - France)
• 5s) Fast and Low Cost HW Bit Map for Memory Test Based on Residue Polynomial System over GF(2)
  Jochen RIVOIR (Verigy Germany GmbH - Germany)
• 65s) Using FPGA configuration memory to accelerate yield learning for advanced process
  JENNY FAN, Ismed Hartanto (Xilinx Inc - USA)

Session 11C- RF Test

• 60s) A Test and Diagnosis Methodology for RF Transceivers
  HUNG-KAI CHEN (ECE NCTU - Taiwan), Chauchin SU (National Chiao Tung University - Taiwan)
• 114s) Fourier Spectrum-Based SignatureTest: A Genetic CAD Framework for Reliable RF Testing Using Low-Performance Test Resources
  GANESH SRINIVASAN (Georgia Institute of Technology - USA), Abhijit CHATTERJEE (Georgia Institute of Technology - USA), VISHWANATH NATARAJAN (Georgia Institute of Technology - USA)
• 12s) A BIST Technique for RF Voltage-Controlled Oscillators
  Hsieh-Hung HSIEH (National Taiwan University - ), Yen-Chih HUANG (National Taiwan University - ), Liang-Hung LU (National Taiwan University - Taiwan)

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E-mail: ats07@ict.ac.cn