IEEE Asian Test Symposium > |
12th Asian Test Symposium, ATS'03
CALL FOR PAPERS ATS '03, The Twelfth Asian Test Symposium, November 16-19, 2003 , Xi'an Hotel, Xi'an, China Submission deadline: May 10, 2003 Notification of acceptance: July 15, 2003 Camera-ready copy: August 15, 2003 Symposium: November 16-19, 2003 Web-page: http://ats03.ict.ac.cn/ Sponsored by IEEE Computer Society Test Technology Technical Council In cooperation with Technical Committee on Fault Tolerant Computing China Computer Federation SCOPE:: The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the World, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the World, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. Topics of interest include, but are not limited to: * Automatic Test Generation * Fault Simulation * Design for Testability * Synthesis for Testability * Built-In Self-Test * On-line Testing * Fault Modeling * Mixed-Signal Test * Design Verification * Economics of Test * Software Testing * Software Design for Test * Electron-Beam Testing * IDDQ Test * System-on-a-Chip Test * Microprocessor Test SUBMISSIONS Regular session: Original technical papers on the above topics are invited. These should not exceed 20 double-spaced pages including figures, and should include a 50-200 word abstract and a list of 4-5 keywords. Authors should include the complete address, phone/fax numbers and email address, and designate a contact person and a presenter. Electronic submissions (PDF or PS files) are strongly recommended. In case of hard copy submission,one should contact to Program Chair for special instructions. Detailed instructions for submissions can be found at the Web-page of ATS'03. The submission will be considered evidence that upon acceptance the author(s) will prepare final manuscript (6 pages for regular session) in time for inclusion in the proceedings and will present the paper at the Symposium. Paper submission by E-mail: ats03@ict.ac.cn KEY DATES Submission deadline: May 10, 2003 Notification of acceptance: July 15, 2003 Camera-ready copy: August 15, 2003 Symposium: November 16-19, 2003 FURTHER INFORMATION: http://ats03.ict.ac.cn/ ORGANIZING COMMITTEE Honorary Chair(s) Yinghua Min Institute of Computing Technology, CAS Email: min(at)ict.ac.cn Hideo Fujiwara Nara Institute of Science and Technology Email: fujiwara(at)is.naist.jp General Co-Chair(s) Xubang Shen Xi'an Microelectronics Technology Inst. Email: shenxubang(at)163.net Zhongcheng Li Institute of Computing Technology, CAS Email: zcli(at)ict.ac.cn Program Co-Chair(s) Xiaowei Li Institute of Computing Technology, CAS Email: lxw(at)ict.ac.cn Masaki Hashizume The University of Tokushima Email: tume(at)ee.tokushima-u.ac.jp Publication Chair Huawei Li Institute of Computing Technology, CAS Email: lihuawei(at)ict.ac.cn Registration Chair Tao Lv Institute of Computing Technology, CAS Email: lvtao(at)ict.ac.cn Finance Chair Jianguo Sun Institute of Computing Technology, CAS jgsun(at)ict.ac.cn Local Arrangement Chair Shi Wang Xi'an Microelectronics Technology Inst. Email: ls-pub(at)mail.xanet.edu.cn Tourism Chair Yongjun Xu Institute of Computing Technology, CAS Email: xyj(at)ict.ac.cn Publicity Chair Yinhe Han Institute of Computing Technology, CAS Email: yinhes(at)ict.ac.cn North American Liaison Xiaoqing Wen SynTest Technologies, Inc. Email: wen(at)syntest.com European Liaison Michel Renovell Email: renovell(at)lirmm.fr Ex Officio ATS Steering Committee Chair Asian and Pacific Group, TTTC IEEE Computer Society Hideo Fujiwara Nara Institute of Science and Technology Email: fujiwara(at)is.naist.jp PROGRAM COMMITTEE Members J.Abraham P.Chaudhuri G.Chen H.Chen K.T.Cheng S.Demidenko Y.Furukawa K.Furuya J.Gao Y.Gong J.Han K.Hatayama T.Hayashi Y.Higami H.Hiraishi S.Kajihara T.Kikuno C.Lee K.Lee H.Li H.Liang F.Lombardi Y.Miura Z.Peng S.M.Reddy A.Orailoglu M.Renovell J.Savir K.K.Saluja W.Shi H.Tamamoto T.Tsuchiya M.Tsunoyama C-L.Wey T.W.Williams C.Wu F.Wu X.Wen S.Xu D.Xiang S.Yang T.Yokohira H.Yokoyama T.Yoneda M.Yoshida S.Huang M.Inoue T.Inoue H.Itoh Y.Zorian A.Ivanov K.Iwasaki S.Takeoka Y.Sun T.Shinogi X.Sun H.Takahashi T.Hosokawa C.Su D.Zhang ------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------- Tutorial (November 16) ---------------------------------------------------------------------------------------------------------------------------------- November 16, 14:00 -17:00 Title: System-on-Chip: Embedded Test in Practice Presenter: Yervant Zorian, Virage Logic Corp., USA Abstract: Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a common paradigm, allowing entire systems to be built on a single chip. This tutorial presents the state-of-the-art in system-level integration and addresses the strategies and current industrial practices in the test of System-on-Chip. It discusses the requirements for test reuse in hierarchical design, such as embedded test strategies for individual cores, test access mechanisms, test interface standardization, optimizing test resource partitioning, and embedded test management and integration at the System-on-Chip level and beyond. Several industrial experiences will be shared with the audience. (This tutorial is part of the IEEE Computer Society TTTC Test Technology Educational Program (TTEP) 2003) Biography: Yervant Zorian is the Vice President and Chief Scientist of Virage Logic Corp. and the Chief Technology Advisor of LogicVision. Previously, he was a Distinguished Member of Technical Staff at Bell Labs, Lucent Technologies. His activities cover the areas of embedded IP cores, SOC and System-in-Package test methodologies. Zorian received an MSc degree from the University of Southern California, and a PhD from McGill University. He is currently the Vice President of IEEE Computer Society and the Editor-in-Chief Emeritus of IEEE Design & Test of Computers. He founded and Chairs the IEEE Workshop on Testing Embedded Core-based System-on-Chip; the IEEE Workshop on Test Resource Partitioning; and the IEEE P1500 Working Group for standardization of embedded core test. He had published three books and several book chapters. He was granted over a dozen patents in the domain of embedded test and repair and received a number of Best Paper Awards. He is an honorary doctor of the National Academy of Sciences of Armenia, a recipient of Distinguished Services Award of IEEE Computer Society, and a Fellow of IEEE. Regular Session ---------------------------------------------------------------------------------------------------------------------------------------------- November 17 ---------------------------------------------------------------------------------------------------------------------------------------------- Plenary Session November 17, 8:30 -10:30 Welcome Message Program Introduction ATS'02 Best Paper Awards presentation Keynote Address: Title: Outstanding Challenges in Testing Nanotechnology Based Integrated Circuits Presenter: Kewal K. Saluja, University of Wisconsin-Madison, USA Abstract: Before we list the outstanding challenges, meaning what remains to be done, we need to ask the following questions: 1) What has changed to require this rethinking? 2) What solutions are still applicable in today¡¦s environment? and 3) What is likely to happen in the future? The answer to the first and the third questions is that the technology is changing (shrinking dimensions) at a very fast rate, without any signs of slowing down. But we also know that this exponential growth rate is not sustainable. What I mean is that the time when slowdown is likely to occur is highly unpredictable. In spite of this uncertainty, we still can use the general growth trends from the past to identify the characteristics of the new problems and describe desirable characteristics of the solutions. It is certain that the complexity of devices has grown. This multidimensional word encompasses area (large ICs and resulting yield and reliability issues), large number of components on a single IC (mixed signal designs, IP cores, and SoC issues), and performance (clock frequency issues) requirements, all in addition to meeting the power demands (peak and average) of the designs. There is no single agreed upon cost metric that satisfies all these requirements. Thus, in general, there are tradeoffs and the solutions that have been proposed target only some aspects. None the less, areas of research that are starting to dominate. The presentation will raise questions in all three dominant domains in the area of testing: traditional issues, power issues, and test application time issues. Biography: Kewal K. Saluja obtained his Bachelor of Engineering (BE) degree in Electrical Engineering from the University of Roorkee, India in 1967, MS and PhD degrees in Electrical and Computer Engineering from the University of Iowa, Iowa City in 1972 and 1973 respectively. He is currently with the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison as a Professor, where he teaches courses in logic design, computer architecture, microprocessor based systems, VLSI design and testing, and fault-tolerant computing. Prior to this, he was at the University of Newcastle, Australia. Over the past two decades, he has developed tools and algorithms for test generation, fault simulation, design for testability and built-in self-test of VLSI digital circuits and systems. His current research interests include testing, sequential circuit test generation, built-in self-test, Iddq testing, test and diagnosis of crosstalk faults, testing RAMs and flash memories, fault-tolerant computing, and sensor networks. He has published over 200 refereed journal and conference papers in these areas. Professor Saluja has held visiting and consulting positions at various institutions. He has also served as a consultant to the United Nations Development Program. He served as an Editor of the IEEE Transactions on Computers (1997-2001), and he is an Associate Editor for the letters section of the Journal of Electronic Testing: Theory and Applications (JETTA). He has served on the program committees of numerous national and international conferences and he was the General Chair of the 29th International Symposium on Fault-Tolerant Computing (FTCS-29). Professor Saluja is a member of Eta Kappa Nu, Tau Beta Pi, a Fellow of the JSPS and a Fellow of the IEEE. Title: Leveraging Infrastructure IP for Yield & Reliability [abstract] Presenter: Yervant Zorian, Virage Logic Corp., USA [biography] Abstract: In addition to the functional IP cores, today¡¦s SOC necessitates embedding a special family of IP blocks, called Infrastructure IP blocks. These are meant to ensure the manufacturability of the SOC and to achieve adequate levels of yield and reliability. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design phase. This keynote address analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such Infrastructure IP. Then, it concentrates on certain examples of such embedded IPs for detection, analysis and correction ------------------------------------------------------------------------------------------------------------------------------------------------ Session 1A: Design for Testability November 17, 11:00 -12:30 Chair: Sudhakar M. Reddy, University of Iowa, USA 1A.1 Reducing Scan Shifts using Folding Scan Trees Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, and Kozo Kinoshita 1A.2 Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning Dong Xiang, Ming-Jing Chen, Jia-guang Sun, and Hideo Fujiwara 1A.3 IC Reliability Simulator ARET and Its Application in Design-For-Reliability Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, and Mark T. Chisa --------------------------------------------- Session 1B: Memory testing 1 November 17, 11:00 -12:30 Chair: Cheng-Wen Wu, National Tsing Hua University, Taiwan 1B.1 Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces Zaid Al-Ars and Ad J. van de Goor 1B.2 Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells Yuki Yamagata, Kenichi Ichino, Masauiki Arail, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Sato, Hiroyuki Itabashi, Takashi Murai, and Nobuyuki Otsuka 1B.3 Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool F. Bertuccelli, F. Bigongiari, A. S. Brogna, G. Di Natale, P. Prinetto, and R. Saletti --------------------------------------------- Session 1C: Fault diagnosis 1 November 17, 11:00 -12:30 Chair: Alex Orailoglu, UCSD, USA 1C.1 Chip-Level Diagnostic Strategy For Full-Scan Designs With Multiple Faults Yu-Chiun Lin and Shi-Yu Huang 1C.2 Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults Yu Huang, Wu-Tung Cheng, Cheng-Ju Hsieh, Huan-Yung Tseng, Alou Huang, and Yu-Ting Hung 1C.3 A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM Comparison Model Xiaofan Yang --------------------------------------------- Session 2A: Delay testing November 17, 14:00 -15:30 Chair: Sandeep K. Gupta, University of Southern California, USA 2A.1 Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models Tsuyoshi Iwagaki, Satoshi Ohtake, and Hideo Fujiwara 2A.2 On Estimation of Fault Efficiency for Path Delay Faults Masayasu Fukunaga, Seiji Kajihara, and Sadami Takeoka 2A.3 Software-Based Delay Fault Testing of Processor Cores Virendra Singh, Michiko Inoue, Kewal K. Saluja, and Hideo Fujiwara 2A.4 A DFT Approach for Path Delay Faults in Interconnected Circuits Irith Pomeranz and Sudhakar M. Reddy --------------------------------------------- Session 2B: BIST November 17, 14:00 -15:30 Chair: Kiyoshi Furuya, Chuo University, Japan 2B.1 Non-Linear Cellular Automata Based PRPG Design (Without Prohibited Pattern Set) In Linear Time Complexity Sukanta Das, Anirban Kundu, Subhayan Sen, Biplab K Sikdar, and P Pal Chaudhuri 2B.2 A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations Ehsan Atoofian and Zainalabedin Navabi 2B.3 A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic Md. Rafiqul Islam, Hafiz Md Hasan Babu, M. Abdur Rahim Mustafa, and Md. Sumon Shahriar --------------------------------------------- Session 2C: Software testing 1 November 17, 14:00 -15:30 Chair: Christian Landrault, LIRMM, France 2C.1 Domain Testing Based on Character String Predicate Ruilian Zhao, Michael R. Lyu, and Yinghua Min 2C.2 Automated TTCN-3 Test Case Generation by means of UML Sequence Diagrams and Markov Chains Matthias Beyer, Winfried Dulz, and Fenhua Zhen 2C.3 Efficiency Analysis & Safety Assessment of Automatic Testing for Safety-critical Software Fangmei Wu and Lei Huang 2C.4 An Expression's Single Fault Model and The Testing Methods Yunzhan Gong, Wanli Xu, and Xiaowei Li --------------------------------------------- Session 3A: Mixed-signal Testing November 17, 16:00 -17:30 Chair: Chin-Long Wey, National Central University, Taiwan 3A.1 PLL Based High Speed Functional Testing Jayasanker Jayabalan, Chee Kiang Goh, Ooi Ban Leong, Leong Mook Seng, Mahadevan K. lyer, and Andrew A.O. Tay 3A.2 Issues related to the formulation of DFT solution for analog circuit test using equivalent fault analysis Mike W. T. Wong 3A.3 A Sigma-Delta Modulation Based BIST for A/D Converters Kuen-Jong Lee, Soon-Jyh Chang, and Ruei-Shiuan Tzeng --------------------------------------------- Session 3B: Test compaction 1 November 17, 16:00 -17:30 Chair: Kewal K. Saluja, University of Wisconsin-Madison, USA 3B.1 A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, and Hideo Fujiwara 3B.2 Optimal Scan Tree Construction with Test Vector Modification for Test Compression Kohei Miyase and Seiji Kajihara 3B.3 STAGE: A Decoding Engine Suitable for Multi-Compressed Test Data Bernd Koenemann --------------------------------------------- Session 3C: RTL verification November 17, 16:00 -17:30 Chair: Jungang Han, Xi'an Institute of Posts&Telecoms, China 3C.1 Automatic Design Validation Framework for HDL Descriptions via RTL ATPG Liang Zhang, Michael Hsiao, and Indradeep Ghosh 3C.2 An Automatic Circuit Extractor for RTL Verification Tun Li, Yang Guo, and Sikun Li 3C.3 An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains Tao Lv, Jianping Fan, and Xiaowei Li -------------------------------------------------------------------------------------------------------------------------------------------- November 18 -------------------------------------------------------------------------------------------------------------------------------------------- Session 4A Enhanced Delay testing and ATPG November 18, 8:30 -10:00 Chair: Debesh K. Das, Jadavpur University, India 4A.1 Delay Testing of MOS Transistor with Gate Oxide Short M. Renovell, J.M. Gallière, F. Azaïs, and Y. Bertrand 4A.2 An enhanced test generator for capacitance induced crosstalk delay faults Arani Sinha, Sandeep K. Gupta, and Melvin A. Breuer 4A.3 Delay Test Pattern Generation considering Crosstalk-induced Effects Huawei Li, Yue Zhang, and Xiaowei Li 4A.4 Automated Test Model Generation from Switch Level Custom Circuits Magdy S. Abadir, Jing Zeng, Carol Pyror, and Juhong Zhu --------------------------------------------- Session 4B: Test Power November 18, 8:30 -10:00 Chair: Chauchin Su, National Chiao Tung Unversity, Taiwan 4B.1 Power Conscious BIST Design for Sequential Circuits using ghost-FSM S Roy and Biplab K Sikdar 4B.2 Average Leakage Current Macromodeling for Dual-threshold Voltage Circuits Yongjun Xu, Zuying Luo, Zhiguo Chen, and Xiaowei Li 4B.3 Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test Ozgur Sinanoglu and Alex Orailoglu --------------------------------------------- Session 4C: Software testing 2 November 18, 8:30 -10:00 Chair: Dafang Zhang, Hunan University, China 4C.1 Analysis of Software Test Item Generation -Comparison between High Skilled and Low Skilled Engineers Masayuki Hirayama, Tetsuya Yamamoto, Osamu Mizuno, and Tohru Kikuno 4C.2 Conformance Test of Distributed Transaction Service Chang Xu and Beihong Jin 4C.3 Build-In-Self-Test for Software Shiyi Xu 4C.4 Testing the Conformity of Transactional Attributes of Components by Simulation HuiQun Zhao, QiXin Gao, and Yuan Gao --------------------------------------------- Session 5A: Fault diagnosis 2 November 18, 10:30 -12:00 Chair: Kaushik Roy, Purdue University, USA 5A.1 Extracting Precise Diagnosis of Bridging Faults From Stuck-at Fault Information Baris Arslan and Alex Orailoglu 5A.2 Fault Diagnosis for Physical Defects of Unknown Behaviors Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, and Kozo Kinoshita 5A.3 Fault Detection for Testable Realizations of Multiple-valued Logic Functions Zhongliang Pan --------------------------------------------- Session 5B: Memory testing 2 November 18, 10:30 -12:00 Chair: Melvin Breuer, University of South California, USA 5B.1 Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders Liugi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, and Simone Borri 5B.2 Defect Oriented Fault Analysis for SRAM Rei-Fu Huang, Yung-Fa Chou, and Cheng-Wen Wu 5B.3 A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM based FPGAs L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, and V. Kamakoti --------------------------------------------- Session 5C: SOC test November 18, 10:30 -12:00 Chair: Yervant Zorian, Virage Logic Corp., USA 5C.1 Between-core Vector Overlapping for Test Cost Reduction in Core Testing Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, and Shinji Tsuruoka 5C.2 A VPI-based Combinational IP Core Module-based Mixed Level Serial Fault Simulation and Test Generation Methodology Pedram A. Riahi, Zainalabedin Navabi, and Fabrizio Lombardi 5C.3 A Test Generation Approach for System-on-Silicon that use Intellectual Property Cores Zhigang Jiang and Sandeep K. Gupta --------------------------------------------- Session 6A: DFT Synthesis November 18, 13:30 -15:00 Chair: Xiaoqing Wen, Syntest Technologies, Inc., USA 6A.1 Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability Hafizur Rahaman, Debesh K. Das, and Bhargab B. Bhattacharya 6A.2 BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability Junhao Shi, Görschwin Fey, and Rolf Drechsler 6A.3 Test Synthesis for Datapaths using Datapath-Controller Functions Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, and Hideo Fujiwara 6A.4 Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis Dong Xiang, Shan Gu, and Hideo Fujiwara --------------------------------------------- Session 6B: Test Scheduling November 18, 13:30 -15:00 Chair: Huawei Li, Institute of Computing Technology, CAS, China 6B.1 Optimal System-on-Chip Test Scheduling Erik Larsson and Hideo Fujiwara 6B.2 SOC Test Time Minimization Under Multiple Constraints Julien Pouget, Erik Larsson, and Zebo Peng 6B.3 Test Time Minimization for Hybrid BIST of Core-Based Systems Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, and Maksim Jenihhin --------------------------------------------- Session 6C: Measurement November 18, 13:30 -15:00 Chair: Michel Renovell, LIRMM, France 6C.1 On-Chip Short-Time Interval Measurement for High-Speed Signal Timing Characterization Tian Xia and Jien-Chung Lo 6C.2 An On-Chip Jitter Measurement Circuit for the PLL Chin-Cheng Tsai and Chung-Len Lee 6C.3 A Low-Cost Jitter Measurement Technique for BIST Applications Jui-Jer Huang and Jiun-Lang Huang 6C.4 Measurement-based Modeling with Adaptive Sampling Junfeng Wang, Jianhua Yang, Gaogang Xie, Mingtian Zhou, and Zhongcheng Li --------------------------------------------- Session 7A: Test economics November 18, 15:30 -17:00 Chair: Jacob Abraham, University of Texas at Austin, USA 7A.1 Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-offs for High-Speed Interconnect Device Testing Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, and Andre Ivanov 7A.2 Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method Yuxin Tian, Michael R. Grimaila, Weiping Shi, and M. Ray Mercer 7A.3 Lowering Cost of Test: Parallel Test or Low-Cost ATE- Jochen Rivoir --------------------------------------------- Session 7B: Memory testing 3 November 18, 15:30 -17:00 Chair: Hideo Tamamoto, Akita University, Japan 7B.1 A Processor-Based Build-In Self-Repair Design for Embedded Memories Chin-Lung Su, Rei-Fu Huang, and Cheng-Wen Wu 7B.2 March SL: A Test For All Static Linked Memory Faults Said Hamdioui, Zaid Al-Ars, Ad J. van de Goor, and Mike Rodgers 7B.3 Test for Delay Faults in Embedded CAMs Xiaogang Du, Joseph Rayhawk, Sudhakar M. Reddy, and Wu-tung Cheng 7B.4 Stress Test for Disturb Faults in Non-volatile Memories Mohammad Gh. Mohammad and Kewal K. Saluja --------------------------------------------- Session 7C: Current test November 18, 15:30 -17:00 Chair: Shi-Yu Huang, National Tsinghua University, Taiwan 7C.1 A BIST Circuit for IDDQ Tests Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, and Kozo Kinoshita 7C.2 At-Speed Current Testing Yinghua Min, Jishun Kuang, and Xiaoyan Niu 7C.3 IDDT ATPG Based on Ambiguous Delay Assignments Jishun Kuang, Yu Wang, Xiaofen Wei, and Changnian Zhang 7C.4 Improvement of Detectability for CMOS Floating Gate Defects in Supply Current Test Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, and Tsutomu Hondo ---------------------------------------------------------------------------------------------------------------------------------------------- November 19 ---------------------------------------------------------------------------------------------------------------------------------------------- Session 8A: SOC DFT November 19, 8:30 -10:00 Chair: Zebo Peng, Linkoping University, Sweden 8A.1 A DFT Selection Method for Reducing Test Application Time of System-on-Chips Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, and Hideo Fujiwara 8A.2 Sharing BIST with Multiple Cores for System-on-a-Chip Huaguo Liang and Cuiyun Jiang 8A.3 Designing Multiple Scan Chains for System-on-Chip (SOC) Md. Staffat Quasem and Sandeep K. Gupta 8A.4 Optimizing Test Access Mechanism under Constrains by Genetic Local Search Algorithm Yingxiang Wang and Weikang Huang --------------------------------------------- Session 8B: Test compaction 2 November 19, 8:30 -10:00 Chair: Andre Ivanov, University of British Columbia, Canada 8B.1 Test Data Volume Reduction by Test Data Realignment Itith Pomeranz and Sudhakar M. Reddy 8B.2 Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, and Anshuman Chandra 8B.3 Test Response Compression Based on Huffman Coding Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, and Tomoo Inoue --------------------------------------------- Session 8C: Functional testing/ Reliability November 19, 8:30 -10:00 Chair: Yasuo Furukawa, ADVANTEST Corp., Japan 8C.1 Probability Model for Faults in Large-Scale Multicomputer Systems Gaocai Wang, Jianer Chen, Guojun Wang, and Songqiao Chen 8C.2 Design Retargetable Platform System for Microprocessor Functional Test Ling Liu, Wennan Feng, Song Jia, Anping Jiang, and Lijiu Ji 8C.3 Assessing software implemented fault detection and fault tolerance Mechanisms P. Gawkowski and J. Sosnowski 8C.4 Briefing a New Approach to Improve the EMI Immunity of DSP Systems Fabian Vargas, Rubem D. R. Fagundes, Daniel Barros Jr., and Diogo B. Brum --------------------------------------------- Session 9A: Formal verification November 19, 10:30 -12:00 Chair: Hiromi Hiraishi, Kyoto Sangyo University, Japan 9A.1 Design Error Diagnosis Based on Verification Techniques Guanghui Li, Ming Shao, and Xiaowei Li 9A.2 SAT-based Algorithm of Verification for Port Order Fault Ming Shao, Guanghui Li, and Xiaowei Li 9A.3 Equivalence Checking Using Independent Cuts Zhan Xu, Xiaolang Yan, Yongjiang Lu, and Haitong Ge --------------------------------------------- Session 9B: Software testing 3 November 19, 10:30 -12:00 Chair: Shiyi Xu, Shanghai University, China 9B.1 A Method to Calculate the Reliability of Component-Based Software Yuan Zhu and Jianhua Gao 9B.2 An Object-Oriented Program Automated Execute Model And The Research of Algorithm Da-Hai Jin and Yun-Zhan Gong 9B.3 User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NT Jin-Min Yang, Da-Fang Zhang, and Xue-Dong Yang Poster Session ----------------------------------------------------------------------------------------------------------------------------------------------- November 19 ------------------------------------------------------------------------------------------------------------------------------------------------ November 19, 10:30 -12:00 P.1 RTL Concurrent Fault Simulation Li Shen P.2 Property Classification for Functional Verification based on CDFG Ming Zhu, Jinian Bian, Weimin Wu, and Hongxi Xue P.3 Error Detection and Correction in VLSI Systems by Online Testing and Retrying JianHui Jiang P.4 Testability Improvement during High-Level Synthesis Saeed Safari, Hadi Esmaeilzadeh, and Amir-Hossein Jahangir P.5 A Test Architecture for System-on-a-Chip Yong-sheng Wang, Li-yi Xiao, Ming-yan Yu, Jin-xiang Wang, and Yi-zheng Ye P.6 Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST Hu He and Yihe Sun P.7 Test Pattern Length Required to Reach the Desired Fault Coverage Junichi Hirase P.8 Damage Size and Software Safety Demonstration Stress Testing Zhongwei Xu and Bangxing Chen P.9 Study on the Cost/Benefit/Optimization of Software Safety Test Meng Li and Zhu Xu --------------------------------------------------------------------------------------------------------------------------------------------- |