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11th Asian Test Symposium, ATS'02
CALL FOR PAPERS
ATS '02, The Eleventh Asian Test Symposium,
November 18-20, 2002
Hyatt Regency Guam, Guam, USA
Submission dealine: April 20, 2002
Web-page: http://ats02.ip.elec.mie-u.ac.jp
Sponsored by
IEEE Computer Society
Test Technology Technical Council
In cooperation with
Technical Group on Fault Tolerant Systems, IEICE
Special Interest Group on System LSI Design Methodology, IPS Japan
SCOPE::
The Asian Test Symposium provides an international forum for engineers
and researchers from all countries of the world, especially from Asia, to
present and discuss various aspects of system, board and device testing
with design, manufacturing and field considerations in mind. The official
language of the symposium is English. Topics of interest include, but are
not limited to:
-Automatic Test Generation / Fault Simulation
-Synthesis for Testability / Design for Testability
-Built-In Self-Test / On-line Testing
-Software Testing / Software Design for Testing
-Fault Modeling & Diagnosis
-Mixed-Signal Test
-Design Verification
-Electron-Beam Testing
-Economics of Test
-Fault Tolerance
-IDDQ Test
-System-on-Chip Test
SUBMISSIONS::
Original technical papers on the above topics are invited. These should
not exceed 20 double-spaced pages including figures, and should include
a 50-200 word abstract and a list of 4 to 5 keywords. Authors should
include the complete address, phone/fax numbers and e-mail address,
and designate a contact person and a presenter. Electronic submissions
(PDF or PS files) are strongly recommended. In case of hardcopy
submission one should contact to Program Chair for special instructions.
Detailed instructions for submissions can be found at the Web-page
of ATS'02. The submission will be considered evidence that upon
acceptance the author(s) will prepare the final manuscript (6 pages
for regular session) in time for inclusion in the proceedings and will
present the paper at the Symposium.
KEY DATES::
Submission deadline: April 20, 2002
Notification of acceptance: July 15, 2002
Camera ready copy: August 15, 2002
Symposium: November 18-20, 2002
FURTHER INFORMATION:
http://ats02.ip.elec.mie-u.ac.jp
E-mail: ats02@ip.elec.mie-u.ac.jp
ORGANIZING COMMITTEE::
General Chair
Kozo Kinoshita
Osaka Gakuin University
General Vice-Chair
Yuzo Takamatsu
Ehime University
Program Chair
Kiyoshi Furuya
Chuo University
Publicity Chair
Tsuyoshi Shinogi
Mie University
Publications Chair
Michiko Inoue
Nara Institute of Science and Technology
Finance Chair
Hiroshi Takahashi
Ehime University
Local Arrangement Chair
Yukiya Miura
Tokyo Metropolitan University
Registration Chair
Yoshinobu Higami
Ehime University
Industrial Arrangement Chair
Toshinori Hosokawa
STARC
Secretary
Seiji Kajihara
Kyushu Institute of Technology
North American Liaison
Andre Ivanov
University of British Columbia
European Liaison
Christian Landrault
LIRMM
Ex Officio
ATS Steering Committee Chair
Asian & Pacific Group
TTTC, IEEE Computer Society
Hideo Fujiwara
Nara Institute of Science and Technology
Program Committee::
A.P. Ambler
Y. Asao
K.O. Boateng
S.T. Chakradhar
H. Date
S. Demidenko
H. Fujioka
Y. Furukawa
A.J. van de Goor
K. Hamaguchi
K. Hashizume
K. Hatayama
T. Hayashi
Y. Iguchi
T. Inoue
N. Itazaki
H. Ito
A. Ivanov
K. Iwasaki
Y. Kakuda
S. Kikuchi
B.C. Kim
Y. Koseko
N. Kuji
C.L. Lee
K.J. Lee
Z. Li
M. Mukuno
K. Nikawa
S. Nishikawa
S. Park
I. Pomeranz
P. Prinetto
E. Prochaska
C.P. Ravikumar
M. Renovell
A. Rubio
K.K. Saluja
T. Sasao
J. Savir
S. Seth
Y. Sugiyama
N. Takagi
S. Takeoka
H. Tamamoto
T. Tsuchiya
M. Tsunoyama
M. Ushikubo
R. Velazco
P. Varma
X. Wen
C.W. Wu
H.J. Wunderlich
S. Xu
S. Yano
T. Yokohira
H. Yokoyama
T. Yoneda
M. Yoshida
D. Zhang
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PLENARY SESSION
November 18
8:30-10:30
Welcome Message: Kozo Kinoshita, General Chair
PC Chair's Message: Kiyoshi Furuya, Program Chair
ATS'01 Best Paper Awards presentation:
Hiromi Hiraishi, ATS'01 Program Chair
TTTC Chair Message and CS/TTTC Award Presentation:
P. Prinetto, TTTC Chair
Keynote Address:
The Current Situation Surrounding EDA, and the Latest Trends
and Themes in EDA Technology
Fumiyasu Hirose, Vice President, Cadence Design Systems,
Japan
REGULAR SESSIONS
November 18
Session 1A: Test Generation
11:00-12:30 Chair:
1A-1 On Generating High Quality Tests for Transition Faults
Yun Shao, Irith Pomeranz, Sudhakar M. Reddy
1A-2 Exact Computation of Maximally Dominating Faults and Its
Application to n-Detection Tests
Ilia Polian, Irith Pomeranz, Bernd Becker
1A-3 Maximum Distance Testing
Shiyi Xu, Jianwen Chen
Session 1B: On-Line Testing
11:00-12:30 Chair:
1B-1 High Precision Result Evaluation of VLSI
Junichi Hirase
1B-2 A Totally Self-Checking Dynamic Asynchronous Datapath
Jing-Ling Yang, Chiu-Sing Choy, Cheong-Fat Chan, Kong-
Pong Pun
1B-3 Non-Intrusive Design of Concurrently Self-Testable FSMs
Petros Drineas, Yiorgos Makris
Session 1C: Analog and Mixed Signal Testing
11:00-12:30 Chair:
1C-1 Test Limitations of Parametric Faults in Analog Circuits
Jacob Savir, Zhen Guo
1C-2 Effects of Amplitude Modulation in Jitter Tolerance
Measurements of Communication Devices
Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma,
Hirobumi Musha
1C-3 On-Chip Analog Response Extraction with 1-Bit Sigma-Delta
Modulators
H. C. Hong, J. L. Huang, K. T. Cheng, C. W. Wu
Session 2A: Test Set Compaction
14:00-15:30 Chair:
2A-1 A State Reduction Method for Non-Scan Based FSM Testing
with Don't Care Inputs Identification Technique
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
2A-2 Improving the Efficiency of Static Compaction Based on
Chronological Order Enumeration of Test Sequences
Irith Pomeranz, Sudhakar M. Reddy
2A-3 Test Data Compression Using Don't-Care Identification and
Statistical Encoding
Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith
Pomeranz, Sudhakar M. Reddy
Session 2B: Design for Testability
14:00-15:30 Chair:
2B-1 Design for Two-Pattern Testability of Controller-Data Path
Circuits
Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
2B-2 MD-SCAN Method for Low Power Scan Testing
Takaki Yoshida, Masafumi Watari
2B-3 Non-Scan Design for Testability based on Fault-oriented
Conflict Analysis
Dong Xiang, Shan Gu, Hideo Fujiwara
Session 2C: Memory Testing 1
14:00-15:30 Chair:
2C-1 Specification and Design of a New Memory Fault Simulator
A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto
2C-2 DRAM Specific Approximation of the Faulty Behavior of Cell
Defects
Zaid Al-Ars, Ad J. van de Goor
2C-3 An Access Timing Measurement Unit of Embedded Memory
Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang
Session 3A: Delay Fault Testing
16:00-17:30 Chair:
3A-1 A Partitioning and Storage Based Built-In Test Pattern
Generation Method for Delay Faults in Scan Circuits
Irith Pomeranz, Sudhakar M. Reddy
3A-2 Optimal Seed Generation for Delay Fault Detection BIST
Lihong Tong, Kazuki Suzuki, Hideo Ito
3A-3 Tap-Delay Measurements for a Digital Delay-Line Used in
High-Speed Inter-Chip Data Communications
Octavian Petre, Hans G. Kerkhoff
Session 3B: Test Synthesis
16:00-17:30 Chair:
3B-1 A Scheduling Method in High-Level Synthesis for Acyclic Partial
Scan Design
Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara
3B-2 Test Requirement Analysis for Low Cost Hierarchical Test Path
Construction
Yiorgos Makris, Alex Orailoglu
3B-3 Testable Realizations for ESOP Expressions of Logic Functions
Pan Zhongliang
Session 3C: Memory Testing 2
16:00-17:30 Chair:
3C-1 DPSC SRAM Transparent Test Algorithm
Hong-Sik Kim, Sungho Kang
3C-2 Tests for Word-Oriented Content Addressable Memories
Zhao Xuemei, Ye Yizheng, Chen Cunxu
3C-3 A High Performance IDDQ Testable Cache for Scaled CMOS
Technologies
Swarup Bhunia, Hai Li, Kaushik Roy
November 19
Session 4A: Crosstalk Fault Testing
8:30-10:30 Chair:
4A-1 Enhanced Crosstalk Fault Models and Methodology to
Generate Tests for Arbitrary Inter-core Interconnect Topology
Wichian Sirisaengtaksin, Sandeep K. Gupta
4A-2 A Testing Scheme for Crosstalk Faults Based on the Oscillation
Test Signal
Ming Shae Wu, Chung Len Lee, Chi Peng Chang, Jwu E
Chen
4A-3 Crosstalk Fault Reduction and Simulation for Clock-Delayed
Domino Circuits
Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita
4A-4 A Concurrent Fault Simulation for Crosstalk Faults in Sequential
Circuit.
Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja
Session 4B: Built-In Self Test 1
8:30-10:30 Chair:
4B-1 Efficient Circuit Specific Pseudoexhaustive Testing with
Cellular Automata
Santanu Chattopadhyay
4B-2 Fault Set Partition for Efficient Width Compression
Emil Gizdarski, Hideo Fujiwara
4B-3 A Reseeding Technique for LFSR-Based BIST Applications
N.-C. Lai, S.-J. Wang
4B-4 A ROMless LFSR Reseeding Scheme for Scan-based BIST
E. Kalligeros, X. Kavousianos, D. Nikolos
Session 4C: Fault-Tolerance
8:30-10:30 Chair:
4C-1 A Fault-Tolerant Architecture for Symmetric Block Ciphers
Min-Kyu Joo, Jin-Hyung Kim, Yoon-Hwa Choi
4C-2 A New Learning Approach to Design Fault Tolerant ANNs:
Finally a Zero HW-SW Overhead
Fabian Vargas, Djones Lettnin, Diogo Brum, Darcio Prestes
4C-3 A New On-Line Robust Approach to Design Noise-Immute
Speech Recognition Systems
Fabian Vargas, Rubem D. R. Fagundes, Daniel Barros Jr.
4C-4 Easily Testable and Fault-Tolerant Design of FFT Butterfly
Networks
Shyue-Kung Lu, Jen-Hong Yeh
Session 5A: Fault Detection and Diagnosis
11:00-12:30 Chair:
5A-1 Fault Detection and Fault Diagnosis Techniques for Lookup
Table FPGA
Shyue-Kung Lu, Jen-Hong Yeh
5A-2 Reduction of Target Fault List for Crosstalk-Induced Delay
Faults by Using Layout Constraints
Keith J. Keller, Hiroshi Takahashi, Kim Le, Kewal K. Saluja,
Yuzo Takamatsu
5A-3 Diagnosis Of Byzantine Open-Segment Faults
Shi-Yu Huang
Session 5B: Built-In Self Test 2
11:00-12:30 Chair:
5B-1 Robust Space Compaction of Test Responses
Alexej Dmitriev, Michael Goessel, Krishnendu Chakrabarty
5B-2 An Evolutionary Design of Pseudo-Random Test Pattern
Generator Without Prohibited Pattern Set (PPS)
Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab
K Sikdar, P Pal Chaudhuri
5B-3 An Embedded Built-In-Self-Test Approach for Analog-to-Digital
Converters
Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang
Session 5C: Software Testing
11:00-12:30 Chair:
5C-1 Statistical Analysis of Time Series Data on the Number of
Faults Detected by Software Testing
Sousuke Amasaki, Takashi Yoshitomi, Osamu Mizuno, Tohru
Kikuno, Yasunari Takagi
5C-2 An Analytic Software Testability Model
Szu-Wen Lin, Jin-Cherng Lin
5C-3 Effective Automated Testing: A Solution of Graphical Object
Verification
Juichi Takahashi, Yoshiaki Kakuda
Session 6: Special Session - Test Strategies and Case
Studies for SoC in Industries
14:00-16:30 Chair & Coordinator:
6-1 At-Speed Built-in Test for Logic Circuits with Multiple Clocks
K. Hatayama, M. Nakao, Y. Sato - Hitachi, Ltd.
6-2 A Test Point Insertion Method to Reduce the Number of Test
Patterns
M. Yoshimura - Matsushita Electric Industrial Co., Ltd., T.
Hosokawa - STARC, M. Ohta - Matsushita Electric Industrial
Co., Ltd.
6-3 A SoC Test Strategy Based on a Non Scan DFT Method
H. Date, T. Hosokawa, M. Muraoka - STARC
6-4 Embedded Test Solution as a Breakthrough in Reducing Cost
of Test for System on Chips
K. Iijima, A. Akar, C. McDonald, D. Burek - LogicVision, Inc.
6-5 Manufacturing Test of SoCs
R. Kapur, T.W. Williams - Synopsys Inc.
6-6 Recent Advances in Test Planning for Modular Testing of Core-
Based SOCs
V. Iyengar - IBM Microelectronics, K. Chakrabarty - Duke
University, E. J. Marinissen - Philips Research Laboratories
November 20
Session 7A: Test Power Reduction
8:30-10:00 Chair:
7A-1 A Method to Reduce Power Dissipation during Test for
Sequential Circuits
Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
7A-2 Test Power Optimization Techniques for CMOS Circuits
Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua
Min
7A-3 Reducing Test Application Time and Power Dissipation for
Scan-Based Testing via Multiple Clock Disabling
Kuen-Jong Lee, Jih-Jeen Chen
Session 7B: System-on-Chip Testing 1
8:30-10:00 Chair:
7B-1 A Simple Wrapped Core Linking Module for SoC Test Access
Jaehoon Song, Sungju Park
7B-2 Testing System-On-Chip by Summations of Cores' Test Output
Voltages
K.Y. Ko, Mike W.T. Wong, Y.S. Lee
7B-3 Test Scheduling of BISTed Memory Cores for SOC
Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang
Cheng, Chih-Tsun Huang, Chen-Wen Wu
Session 7C: Verification and Simulation
8:30-10:00 Chair:
7C-1 Effective Error Diagnosis for RTL Designs in HDLs
Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou
7C-2 Evolutionary Test Program Induction for Microprocessor Design
Verification
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda,
Giovanni Squillero
7C-3 Hierarchical Fault Simulation Using Behavioral and Gate Level
Hardware Models
Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi
Session 8A: Test Systems
10:30-12:00 Chair:
8A-1 Testing Embedded Systems by Using a C++ Script Interpreter
Harald J. Zainzinger
8A-2 Extending EDA Environment from Design to Test
Rochit Rajsuman
8A-3 Vector Memory Expansion System For T33XX Logic Tester
Kazuhiro Yamada, Yoshikazu Takahashi
Session 8B: System-on-Chip Testing 2
10:30-12:00 Chair:
8B-1 Integrated Test Scheduling, Test Parallelization and TAM Design
Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
8B-2 Core - Clustering Based SOC Test Scheduling Optimization
Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng
8B-3 Test Scheduling and Test Access Architecture Optimization
for System-on-Chips
Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-
Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu
Session 8C: Current Testing
10:30-12:00 Chair:
8C-1 CMOS Floating Gate Defect Detection Using IDDQ Test with
DC Power Supply Superposed by AC Component
H. Michinishi, T. Yokohira, T. Okamoto, T. Kobayashi, T. Hondo
8C-2 Test Time Reduction for IDDQ testing by Arranging Test Vectors
Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi
Tamesada
8C-3 Time Slot Specification Based Approach to Analog Fault
Diagnosis Using Built-in Current Sensor and Test Point Insertion
Shambuhu Upadihyaya, Jae Min Lee, Padmanabhan Nair
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