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10th Asian Test Symposium, ATS'01
The Tenth Asian Test Symposium (ATS'01) November 19-21, 2001, Rihga Royal Hotel Kyoto, Kyoto, Japan Sponsored by IEEE Computer Cociety, TTTC In cooperation with Technical Group on Fault Tolerant Systems, IEICE Special Interest Group on System LSI Design Methodology, IPS Japan SCOPE The Asian Test Symposium provides an international forum for engineers and researchers from all countries of the world, especially from Asia, to present and discuss various aspects of system, board and device testing with design, manufacturing and field considerations in mind. The official language of the symposium is English. Topics of interest include, but are not limited to: Automatic Test Generation / Fault Simulation Synthesis for Testability / Design for Testability Built-In Self-Test / On-line Testing Software Testing / Software Design for Testing Fault Modeling & Diagnosis Mixed-Signal Test Design Verification Electron-Beam Testing Economics of Test Fault Tolerance IDDQ Test System-on-Chip Test SUBMISSIONS Regular session: Original technical papers on the above topics are invited. These should not exceed 20 double-spaced pages including figures, and should include a 50-200 word abstract and a list of 4 to 5 keywords. Authors should include the complete address, phone/fax numbers and e-mail address, and designate a contact person and a presenter. Electronic submissions (PDF or PS files) are preferred. In case of hardcopy submission one may contact to Program Chair for special instructions. Regular paper submission: http://www.ats01.kyoto-su.ac.jp/submit.html Poster session: Industrial poster session regarding DFT application to real chips is planned. An abstract of around 200 words is required for submission. The submissions should include the complete address, phone/fax numbers and e-mail address, and designate a contact person and a presenter. Poster submission : http://www.ats01.kyoto-su.ac.jp/poster.html Detailed instructions for submissions can be found at the Web-page: http://ats01.dsgn.im.hiroshima-cu.ac.jp . The submission will be considered evidence that upon acceptance the author(s) will prepare the final manuscript (6 pages for regular session and 1 page for poster session) in time for inclusion in the proceedings and will present the paper at the Symposium. AWARDS ATS'01 will present a best paper award. And The Tenth Anniversary Committee of ATS will give Professor Teruhiko Yamada Memorial Award (Travel Grant and Plaque) to 4 to 6 students submitting high quality paper. Student must apply the award when submitting his paper. Detailed information on Professor Teruhiko Yamada Memorial Award can be found at: http://ats01.dsgn.im.hiroshima-cu.ac.jp/yamada-awards.html -------- TUTORIAL SESSIONS The following two half-day tutorial sessions are planned. 1. Testing Embedded-Core-Based System Chips Erik Jan Marinissen and Yervant Zorian 2. Testing Memories and Embedded Memory Cores: Fault Models, Algorithms, DFT, BIST, BISR and Industrial Results Ad J. van de Goor -------- Sponsored by IEEE Computer Society http://www.computer.org/ Test Technology Technical Council http://www.computer.org/tab/tttc/ In cooperation with Technical Group on Fault Tolerant Systems, IEICE http://www.ieice.or.jp/iss/fts/index.html Special Interest Group on System LSI Design Methodology, IPS Japan http://www.elc.ees.saitama-u.ac.jp/SLDM/ -------- Organizing Committee Symposium Chair Kiyoshi Furuya Chuo University furuya(at)ise.chuo-u.ac.jp Program Chair Hiromi Hiraishi Kyoto Sangyo University hiraishi(at)ics.kyoto-su.ac.jp Program Vice-chair Kazumi Hatayama Hitachi Ltd. k-hataya(at)crl.hitachi.co.jp Publicity Chair Tomoo Inoue Hiroshima City University tomoo(at)im.hiroshima-cu.ac.jp Publications Chair Hideo Tamamoto Akita University tamamoto(at)ie.akita-u.ac.jp Finance Chair Seiji Kajihara Kyushu Institute of Technology kajihara(at)cse.kyutech.ac.jp Local Arrangement Chair Tohru Kikuno Osaka University kikuno(at)ics.es.osaka-u.ac.jp Local Arrangement Vice-chair Akira Motohara Matsushita Electric Industrial Co. Ltd. motohara(at)ngk.csdd.mei.co.jp Registration Chair Terumine Hayashi Mie University hayashi(at)hayashi.elec.mie-u.ac.jp Industrial Arrangement Chair Masaaki Yoshida NEC Corporation myos(at)lsi.nec.co.jp Secretary Yukihiro Iguchi Meiji University iguchi(at)cs.meiji.ac.jp USA Liaison Vishwani D. Agrawal Agere Systems va(at)agere.com European Liaison Christian Landrault LIRMM landrault(at)lirmm.fr Ex Officio Asian & Pacific Group Chair TTTC, IEEE Computer Society Kozo Kinoshita Osaka Gakuin University kozo(at)utc.osaka-gu.ac.jp Program Committee A.P. Ambler Y. Asao S.T. Chakradhar H. Date S. Demidenko H. Fujioka Y. Furukawa A.J. van de Goor K. Hamaguchi M. Hashizume T. Hosokawa M. Inoue N. Itazaki H. Ito A. Ivanov K. Iwasaki Y. Kakuda B. Kaminska N. Kamiura S. Kikuchi Y. Koseko N. Kuji C.L. Lee K.J. Lee Z. Li Y. Miura M. Mukuno T. Nakata K. Nikawa S. Nishikawa S. Park I. Pomeranz P. Prinetto E. Prochaska C.P. Ravikumar M. Renovell A. Rubio K.K. Saluja T. Sasao J. Savir S. Seth T. Shinogi T. Sugawara Y. Sugiyama N. Takagi Y. Takahashi M. Tsunoyama M. Ushikubo P. Varma X. Wen C.W. Wu H.J. Wunderlich S. Xu S. Yano T. Yokohira H. Yokoyama T. Yoneda D. Zhang ------------------------------------------------------------------ TECHNICAL SESSIONS [Tutorial session] [Regular session] [Poster session] Tutorials Nov. 19 Tutorial 1 9:30-12:30 "Testing Memories and Embedded Memory Cores: Fault Models, Algorithms, DFT, BIST, BISR and Industrial Results" by A. J. van de Goor - Delft University of Technology, The Netherlands Abstract: Microprocessors, large ASICs and SoC designs contain, in addition to logic, also many embedded memories. Because of this, the subject of testing (embedded) memories will be addressed in this tutorial. After a global introduction, classical memory fault models and march tests are introduced. It will be shown why specific faults are covered by a given test. An overview of the fault coverage of a large set of well-known march tests will be presented. Design-for testability (DFT), in terms of Weak Write mode, will be presented, followed by a classification of Built-In Self-Test (BIST) approaches. An industrial example will be presented for each BIST class. Next, the concepts, advantages/disadvantages of Built-In Self-Repair (BISR) will be presented, together with industrial applications. Last, an industrial evaluation of a large set of tests, applied to a large number of DRAM chips, will be presented, together with a strategy for designing an optimal set of tests. The main modules of the tutorial are: 1. Introduction, 2. Memory fault models and march tests, 3. DFT, BIST and BISR, and 4. Test strategy. Tutorial 2 14:00-17:00 "Testing Embedded-Core-Based System Chips" by E. J. Marinissen - Philips Research, The Netherlands and Y. Zorian - LogicVision, USA Abstract: Advances in semiconductor technologies enable the design and manufacturing of complex system-on-chip. These complex chips contain embedded pre-designed modules called cores. This tutorial provides an introduction into the motivation of core-based design and test development, highlights the new challenges related to core-based testing, and gives an overview of current industrial and academic practices in this domain. We summarize the current status of industry-wide efforts and standardization in IEEE P1500 Standard for Embedded Core Test and the VSI Alliance. The main modules of the tutorial are 1. Challenges in Embedded-Core Test, 2. Architectural Elements for Core Test Access, 3. Standardization Efforts, 4. SOC Testability Process, Tools, and Flows, and 5. Industrial Experiences. Regular Sessions Nov. 20 Plenary Session 8:30 - 10:00 Welcome Message: K. Furuya, General Chair Program Introduction: H. Hiraishi, Program Chair Tenth Anniversary Committee Chair message and Teruhiko Yamada Memorial Awards presentation: K. Kinoshita, Tenth Anniversary Committee Chair ATS'00 Best Paper Awards presentation: K.-J. Lee, ATS'00 Program Chair TTTC Chair Message and CS/TTTC Award Presentation: P. Prinetto, TTTC Chair Keynote Address: DFT for High Quality Low Cost Manufacturing Test Janusz Rajski, Mentor Graphics Corporation, USA Session 1A Design for Testability 10:30 - 12:00 Chair: Ermenfried Prochaska - Fachhochschule Heilbronn, Germany 1A.1 Design for Hierarchical Two-Pattern Testability of Data Paths M. A. U. Amin, S. Ohtake, H. Fujiwara - Nara Institute of Science and Technology, Japan 1A.2 A Multiple Phase Partial Scan Design Method D. Xiang, Y. Xu - Tsinghua Univ., China 1A.3 Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States H. Yotsuyanagi, S. Hata, M. Hashizume, T. Tamesada - The Univ. of Tokushima, Japan Session 1B Fault Modeling for Memories 10:30 - 12:00 Chair: Kazuhiko Iwasaki - Tokyo Metropolitan University, Japan 1B.1 Tests for Resistive and Capacitive Defects in Address Decoders M. Klaus - ProMOS Technologies, Taiwan, A. J. van de Goor - Delft Univ. of Technology, The Netherlands 1B.2 Detecting Unique Faults in Multi-Port SRAMs S. Hamdioui, A. J. van de Goor - Delft Univ. of Technology, The Netherlands, D. Eastwick, M. Rodgers - Intel Corporation, USA 1B.3 A Memory Specific Notation for Fault Modeling Z. Al-Ars, A. J. van de Goor - Delft Univ. of Technology, The Netherlands, J. Braun, D. Richter - Infineon Technologies, Germany Session 1C Diagnosis 10:30 - 12:00 Chair: Shiyi Xu - Shanghai University, China 1C.1 On Pass/Fail Dictionaries for Scan Circuits I. Pomeranz - Purdue Univ., USA 1C.2 Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA. M. Go"ssel, V. Ocheretnij - Univ. of Potsdam, Germany, S. Chakrabarty - Kalyani Univ., India 1C.3 Simulation-based Diagnosis for Crosstalk Faults in Sequential Circuits H. Takahashi - Ehime Univ., Japan, M. Phadoongsidhi - Univ. of Wisconsin-Madison, USA, Y. Higami - Ehime Univ., Japan, K. K. Saluja - Univ. of Wisconsin-Madison, USA, Y. Takamatsu - Ehime Univ., Japan Session 2A ATPG 13:30 - 15:00 Chair: Christian Landrault - LIRMM, France 2A.1 Test Generation for Double Struck-at Faults Y. Higami, N. Takahashi, Y. Takamatsu - Ehime Univ., Japan 2A.2 Faulty Resistance Sectioning Technique for Resistive Bridging Fault ATPG Systems T. Shinogi, T. Kanbayashi, T. Yoshikawa, S. Tsuruoka, T. Hayashi - Mie Univ., Japan 2A.3 On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits R. Guo - Intel Corp., USA, S. M. Reddy - Univ. of Iowa, USA, I. Pomeranz - Purdue Univ., USA Session 2B Embedded Memory Test 13:30 - 15:00 Chair: Yervant Zorian - LogicVision, Inc., USA 2B.1 Automatic Generation of Memory Built-In Self-Test Cores for System-on-Chip K. L. Cheng, C. M. Hsueh, J. R. Huang, J. C. Yeh, C. T. Huang, C. W. Wu - National Tsing Hua Univ., Taiwan 2B.2 A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis D. Appello - STMicroelectronics, F. Corno, M. Giovinetto, M. Rebaudengo, M. Sonza Reorda - Politecnico di Torino, Italy 2B.3 A Built-In Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters C. W. Wang, R. S. Tzeng, C. F. Wu, C.T. Huang, C. W. Wu, S. Y. Huang - National Tsing Hua Univ., Taiwan, S. H. Lin, H. P. Wang - SynTest Technologies, Inc., Taiwan Session 2C IDDQ Test and Diagnosis 13:30 - 15:00 Chair: Hiroshi Yokoyama - Akita University, Japan 2C.1 IDDQ Sensing Technique for High Speed IDDQ Testing T. Takeda, M. Hashizume, M. Ichimiya, H. Yotsuyanagi - The Univ. of Tokushima, Japan, Y. Miura - Tokyo Metropolitan Univ., Japan, K. Kinoshita - Osaka Gakuin Univ., Japan 2C.2 CMOS Open Defect Detection Based on Supply Current in Time-Variable Electric Field and Supply Voltage Application M. Hashizume, M. Ichimiya, H. Yotsuyanagi, T. Tamesada - The Univ. of Tokushima, Japan 2C.3 An Approach to Improve the Resolution of Defect-Based Diagnosis I. Yamazaki, H. Yamanaka, T. Ikeda - Hitachi, Ltd., Japan, M. Takakura - Hitachi Engineering Co., Ltd., Japan, Y. Sato - Hitachi, Ltd., Japan Session 3A Test Compaction 16:00 - 17:30 Chair: Toshinori Hosokawa - Semiconductor Technology Academic Research Center, Japan 3A.1 A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits I. Pomeranz - Purdue Univ., USA, S. M. Reddy - Univ. of Iowa, USA 3A.2 A Method of Static Compaction of Test Stimuli K. O. Boateng - Fujitsu Laboratories Ltd., Japan, H. Konishi - Fujitsu Co., Japan, T. Nakata - Fujitsu Laboratories Ltd., Japan 3A.3 Dynamic Test Compression Using Statistical Coding H. Ichihara, A. Ogawa, T. Inoue, A. Tamura - Hiroshima City Univ., Japan Session 3B Pattern Generation for Memory Test 16:00 - 17:30 Chair: Tetsuo Tada - Mitsubishi Electric Corporation, Japan 3B.1 Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing M. J. Wang, R. L. Jiang, J. W. Hsia - Vanguard International Semiconductor Corporation, Taiwan, C. H. Wang, J. E. Chen - Chung-Hua Univ., Taiwan 3B.2 Memory Read Faults: Taxonomy and Automatic Test Generation A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto - Politecnico di Torino, Italy 3B.3 Simulation and Development of Short Transparent Tests for RAM S. Demidenko - Massey Univ., New Zealand, A. van de Goor - Delft Univ. of Technology, The Netherlands, S. Henderson - Massey Univ., New Zealand, P. Knoppers - Delft Univ. of Technology, The Netherlands Session 3C Virtual Tester and Beam Testing 16:00 - 17:30 Chair: Koji Nakamae - Osaka University, Japan 3C.1 Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions J. Hirase - Matsushita Electric Industrial Co., Ltd., Japan 3C.2 EB-Testing-Pad Method and its Evaluation by Actual Devices N. Kuji - NTT Electronics Co., Japan, T. Ishihara - NTT Telecommunications Energy Laboratories, Japan 3C.3 Benefits of Phase Interference Detection to IC Waveform Probing T. Ishikawa - Schlumberger Semiconductor Solutions, Japan, J. A. Block- Schlumberger SABER, USA, W. K. Lo, C. Shaw - Schlumberger Probe Systems, USA Nov. 21 Session 4A SoC Test Access Mechanism 8:30 - 10:00 Chair: Hiroshi Date - ABEL Systems Inc., Japan 4A.1 A DFT Method for Core-Based Systems-on-a-Chip based on Consecutive Testability T. Yoneda, H. Fujiwara - Nara Institute of Science and Technology, Japan 4A.2 Compaction Schemes with Minimum Test Application Time O. Sinanoglu, A. Orailoglu - Univ. of California, San Diego, USA 4A.3 Design of an Optimal Test Access Architecture Using a Genetic Algorithm Z. S. Ebadi, A. Ivanov - The Univ. of British Columbia, Canada Session 4B RTL ATPG 8:30 - 10:00 Chair: Jacob A. Abraham - University of Texas at Austin, USA 4B.1 An RT-level ATPG Based on Clustering of Circuit States H. Li, Y. Min, Z. Li - Chinese Academy of Sciences, China 4B.2 An Approach to RTL Fault Extraction and Test Generation Z. Yin, Y. Min, X. Li - Chinese Academy of Sciences, China 4B.3 Effective Techniques for High-Level ATPG F. Corno, G. Cumani, M. Sonza Reorda, G. Squillero - Politecnico di Torino, Italy Session 4C Delay Test 8:30 - 10:00 Chair: Jacob Savir - New Jersey Institute of Technology, USA 4C.1 An Efficient Method to Identify Untestable Path Delay Faults Y. Shao, S. M. Reddy - Univ. of Iowa, USA, S. Kajihara - Kyushu Institute of Technology, Japan, I. Pomeranz - Purdue Univ., USA 4C.2 SpeedGrade: An RTL Path Delay Fault Simulator K. S. Kim, R. Jayabharathi, C. Carstens - Intel Corporation, USA 4C.3 Test Generation for Multiple-Threshold Gate Delay Fault Model M. Nakao, Y. Kiyoshige, K. Hatayama, Y. Sato, T. Nagumo - Hitachi, Ltd., Japan Session 5A SoC Test Scheduling 11:00 - 12:30 Chair: Prab Varma - Veritable Inc., USA 5A.1 A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch - LIRMM / CNRS, France 5A.2 Test Scheduling and Scan-Chain Division Under Power Constraint E. Larsson, Z. Peng - Link#246;pings Univ., Sweden 5A.3 Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design Y. Huang - Univ. of Iowa, USA, W. T. Cheng, C. C. Tsai, N. Mukherjee, O. Samman, Y. Zaidan - Mentor Graphics Corporation, USA, S. M. Reddy - Univ. of Iowa, USA Session 5B FSM Test 11:00 - 12:30 Chair: Hiroshi Takahashi - Ehime University, Japan 5B.1 A Unified Scheme for Designing Testable State Machines P. K. Lala - Univ. of Arkansas, USA, A. Walker - North Carolina A&T State Univ., USA 5B.2 Generation of an Ordered Sequence of Test Vectors for Single State Transition Faults in Large Sequential Machines S. Goswami, A. Chanda, D. Roy Choudhury - Indian Institute of Technology, Kharagpur, India 5B.3 Enhancing BIST Quality of Sequential Machines Through Degree-of-freedom Analysis B. K. Sikdar - Bengal Engineering College (D U), India, S. Roy - Kalyani Govt. Engineering College, India, D. K. Das - Jadavpur Univ., India Session 5C On-line Testing and Fault Injection 11:00 - 12:30 Chair: Masahiro Tsunoyama - Niigata Institute of Technology, Japan 5C.1 Robust Self Concurrent Test of Linear Digital Systems E. Simeu, A. Abdelhay, M. A. Naal - TIMA Laboratory, France 5C.2 Control-Flow Checking via Regular Expressions A. Benso, S. Di Carlo, G. Di Natale, P. Prinetto, L. Tagliaferri - Politecnico di Torino, Italy 5C.3 FPGA-based Fault Injection for Microprocessor Systems P. Civera, L. Macchiarulo, M. Rebaudengo, M. Sonza Reorda, M. Violante - Politecnico di Torino, Italy Session 6A Advances in BIST 14:00 - 15:30 Chair: Kazuhiko Iijima - LogicVision, Inc., Japan 6A.1 A BIST Based on Concurrent Single-Control Testability of RTL Data Paths K. Yamaguchi - Nara Institute of Science and Technology, Japan, H. Wada - Hitachi, Ltd., Japan, T. Masuzawa - Osaka Univ., Japan, H. Fujiwara - Nara Institute of Science and Technology, Japan 6A.2 Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit S. Almukhaizim, P. Petrov, A. Orailoglu - Univ. of California, San Diego, USA 6A.3 A SmartBIST Variant with Guaranteed Encoding B. Koenemann, C. Barnhart, B. Keller, T. Snethen, O. Farnsworth, D. Wheater - IBM Microelectronics, USA Session 6B Analog Test 14:00 - 15:30 Chair: Yasuo Furukawa - Advantest Corporation, Japan 6B.1 MEMS Comb-Actuator Resonance Measurement Method Using the 2nd Harmonic of the GND Current Y. Takahashi - IBM Japan, Japan 6B.2 On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks Z. Guo, X. M. Zhang, J. Savir, Y. Q. Shi - New Jersey Institute of Technology, USA 6B.3 Specification Based Digital Compatible Built-In Test of Embedded Analog Circuits A. Halder, A. Chatterjee - Georgia Institute of Technology, USA Session 6C Fault Tolerance 14:00 - 15:30 Chair: Hideo Ito - Chiba University, Japan 6C.1 Yield Increase of VLSI after Redundancy-repeating J. Hirase - Matsushita Electric Industrial Co., Ltd., Japan 6C.2 An Improvement in Weight-Fault Tolerance of Feedforward Neural Networks N. Kamiura - Himeji Institute of Technology, Japan, Y. Taniguchi - Sharp Corporation, Japan, T. Isokawa, N. Matsui - Himeji Institute of Technology, Japan 6C.3 A New Code-disjoint Sum-bit Duplicated Carry Look-ahead Adder for Parity Codes E. S. Sogomonyan, V. Ocheretnij, M. G#246;ssel - Univ. of Potsdam, Germany Session 7A Various Ideas for BIST 16:00 - 18:00 Chair: Tokumi Yokohira - Okayama University, Japan 7A.1 Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck? I. Bayraktaroglu, A. Orailoglu - Univ. of California, San Diego, USA 7A.2 Hybrid BIST Using Partially Rotational Scan K. Ichino, T. Asakawa, S. Fukumoto, K. Iwasaki - Tokyo Metropolitan Univ., Japan, S. Kajihara - Kyusyu Institute of Technology, Japan 7A.3 Multiple Attractor Cellular Automata for Hierarchical Diagnosis of VLSI Circuits B. K. Sikdar - Bengal Engineering College (D U), India, N. Ganguly - IISWBM, Calcutta, India, A. Karmakar, S. S. Chowdhury, P. P. Chaudhuri - Bengal Engineering College (D U), India 7A.4* A Microcode-Based Memory BIST Implementing Modified March Algorithm D. Youn, T. Kim, S. Park - Hanyang Univ., Korea 7A.5* Fault Simulation for VHDL Based Test Bench and BIST Evaluation H. Farshbaf, M. Zolfy, S. Mirkhani, Z. Navabi - Univ. of Tehran, Iran Session 7B Analog/Mixed Signal Test 16:00 - 18:00 Chair: Michel Renovell - LIRMM, France 7B.1 Automatic Test Generation for Analog Circuits Using Compact Test Transfer Function Models B. Sahu, A. Chatterjee - Georgia Institute of Technology, USA 7B.2 Distance Constrained Dimensionality Reduction for Parametric Fault Test Generator A. V. Gomes, A. Chatterjee - Georgia Institute of Technology, USA 7B.3 Short Circuit Faults in State-Of-The-Art ADCs - Are They Hard or Soft? A. Lechner, A. Richardson - Lancaster Univ., UK, B. Hermes - Philips Semiconductors, UK 7B.4 An Embedded Built-In-Self-Test Approach for Digital-to-Analog Converters J. H. Tsai, M. J. Hsiao, T. Y. Chang - National Tsing Hua Univ., Taiwan Session 7C Verification 16:00 - 18:00 Chair: Kiyoharu Hamaguchi - Osaka University, Japan 7C.1 An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model C. Y. Wang, S. W. Tung, J. Y. Jou - National Chiao Tung Univ., Taiwan 7C.2 Framework of Timed Trace Theoretic Verification Revisited B. Zhou - Cadence Design Systems, Japan, T. Yoneda - Tokyo Institute of Technology, Japan, C. Myers - Univ. of Utah, USA 7C.3 Efficient Pattern-Based Verification of Connections to IP Cores I. Polian, W.G. Gnther, B. Bekker- Albert-Ludwigs-Univ. of Freiburg, Germany 7C.4 Design Verification and Robust Design Technique for Cross-Talk Faults B. C. Paul, S. H. Choi, Y. Im, K. Roy - Purdue Univ., USA Poster Session Nov. 20 Session 1 DFT Application to Real chips 1. A Practical Logic BIST for ASIC Designs Y. Sato, M. Sato, K. Tsutsumida, T. Ikeya, M. Kawashima (Hitachi, Ltd.) 2. TX7901 DFT T. Kamada (Toshiba Corporation) 3. An Application of Partial Scan Techniques to a High-End System LSI Design T. Ono (NEC Corporation), A. Kozawa, T. Kimura, Y. Konno (NEC Software Hokuriku, Ltd.), K. Saga (NEC Corporation) 4. Built-Out Self-Test (BOST) for Analog Circuits in a System LSI: Test Solution to Reduce Test Costs H. Hanai, S. Yamada, H. Mori, E. Yamashita, T. Funakura (Mitsubishi Electric Corporation) 5. High-Speed Interface Testing M. Suzuki, R. Shimizu, N. Naka, K. Nakamura (Fujitsu Ltd.) 6. A New Inter-Core Built-In-Self-Test Circuits for Tri-state Buffers in the System on a Chip T. Kishi, M. Ohta, T. Taniguchi, H. Kadota (Matsushita Electric Industrial Co., Ltd.) 7. A Flexible Logic BIST Scheme and Its Application to SoC Designs X. Wen, H-P. Wang (Syntest Technologies, Inc.) Nov. 21 Session 2 Practical Ideas from Universities 1. Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan I. Pomeranz (Purdue Univ.), S. M. Reddy (Univ. of Iowa), X. Lin (Mentor Graphics Corp.) 2. Non-Exhaustive Parity Testing S. Xu (Shanghai Univ.) 3. Built-In Self-Test for State Faults Induced by Crosstalk in Sequential Circuits K. Shimizu, N. Itazaki (Osaka Univ.), K. Kinoshita (Osaka Gakuin Univ.) 4. A Low-Power LFSR Architecture T. C. Huang, K. J. Lee (National Cheng-Kung Univ.) ------------------------------------------------------------------- |